T-SeriesのトピックRe: T2080 processor DDR3 initilalization

T2080 processor DDR3 initilalization

vijaikumar — Mon, 10 Aug 2015 13:03:49 GMT

Hi All,

We have designed a custom T2080 board based on T2080RDB reference design. Our Board has a soldered down DDR instead of a DIMM based found in reference design. We donot have an eeprom with SPD details. I see that the u-boot uses SPD data from DIMM for initializing the DDR on T2080RDB. How can I initialize the DDR using u-boot in my custom board?

Regards

Vijai

Re: T2080 processor DDR3 initilalization

LPP — Wed, 12 Aug 2015 08:01:50 GMT

u-boot provides an option for the non-SPD initialization:"#if !defined(CONFIG_DDR_SPD)"

Please refer to target board initialization file ( for example, u-boot\board\freescale\p2020ds\p020ds.c)

The values are defined in u-boot\include\configs\p020ds.h

Actual values depend on the design.

Freescale provides application note about DDR registers settings.

http://cache.freescale.com/files/32bit/doc/app_note/AN4039.pdf

Also, the DDR (Double Data Rate RAM Memory) Validation tool (DDRv) is a software application that helps you “tune” the DDR settings that can be the most difficult to get "centered."

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=PE_QORIQ_DDRV

Have a great day,
Pavel

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Re: T2080 processor DDR3 initilalization

vijaikumar — Wed, 12 Aug 2015 09:50:53 GMT

Hi Pavel,

Thank you for your reply. Currently we are loading the RCW file from NAND. From T2080 Reference Manual, I understand that once a RCW file is loaded the processor should release the HRESET line. In our case the HRESET line is not being released, and we are unable proceed further. Can you suggest a way to debug this issue. I am also wondering what is the minimum RCW fields need to be configured properly in order for the processor to release the reset line.

Re: T2080 processor DDR3 initilalization

sinanakman — Wed, 12 Aug 2015 15:35:20 GMT

Hi Vijai

AFAIK, there are 3 potential main causes for HRESET not

being released related to your case :

- PORESET_B is not deasserted by your external reset logic

- IFC NAND Flash interface reports an ECC error (when it

is configured as the RCW source)

- PBL reports an error while loading the RCW data

So in your case you can perhaps verify if any of the above

happens.

Pavel can probably shed more light into this.

Hope this helps

Regards

Sinan Akman

Re: T2080 processor DDR3 initilalization

flabyjacob — Tue, 22 Sep 2015 06:50:28 GMT

Hi Pavel

I would like to ask something on the DDR3 initialization for the custom t2080 board what Vijai had posted before.

I could not see "#if !defined(CONFIG_DDR_SPD)" in my UBoot source folder.

Can you please tell me where can I find it.

If it is not there how can I initialize DDR in UBoot since our custom board doen not have a DIMM module

Regards,

Flaby

Re: T2080 processor DDR3 initilalization

LPP — Tue, 22 Sep 2015 10:03:55 GMT

DDR parameters are defined in board configuration file. You can find specific file at the path \git\include\configs

For example, T208xRDB.h file contains "#define CONFIG_DDR_SPD" since this board supports SODIM.

On the contrary, P1023RDS.h file provides the following comment with the following settings of DDR parameters:

"/* These are used when DDR doesn't use SPD. */ "

#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */

...

Re: T2080 processor DDR3 initilalization

flabyjacob — Thu, 24 Sep 2015 04:53:56 GMT

Hi Pavel,

Thanks a lot for your response...

We are able to initialize DDR3 of the custom t2080 board from UBoot and its up...

Regards,

Flaby

Re: T2080 processor DDR3 initilalization

vidyasagartata — Fri, 26 May 2017 06:52:07 GMT

Hi All,

Same issue facing in the 32 bit DDR3 discrete chip configuration in t2080 SDK2.0

Please suggest where modification is required.

Thanks,

Vidya