T1024 Second Core Bootup

kushshah — Thu, 11 Oct 2018 13:47:27 GMT

Hello Team,

Does MMU for core-1 has default 4 KB page defined at 0x0_FFFF_Fnnn even when boot space translation is enabled? or Does MMU provides access for the page which is set it up by the Boot space translation register low (LCC_BSTRL)?

Can we set up TLB entry for the page defined in LCC_BSTRL for core-1 from core-0 before releasing the core-1?

I have referred u-boot code (mp.c), in that they are disabling the default reset page TLB and set it up that TLB with the page which will set up by LCC_BSTRL. Does default TLB entry is global for both cores?

Re: T1024 Second Core Bootup

yipingwang — Mon, 29 Oct 2018 05:38:27 GMT

Hello Kush Shah,

When each core comes out of reset, its MMU has one 4KB page defined at 0x0_FFFF_Fnnn. Each core begins execution with the instruction at the effective address 0x0_FFFF_FFFC.

To boot space translation mechanism allows translation of this window(in physical address space) to one specified by BSTRH, BSTRL and BSTAR. Processor will fetch first instruction from effective address 0xFFFF_FFFC as usual, the boot space translation mechanism will translate the physical address to the specific address such as 0x6_0000_0FFC.

Each core has its own default 4K TLB entry, the boot space translation affects transactions initiated by all cores in the same manner.

Have a great day,
TIC

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T-SeriesのトピックRe: T1024 Second Core Bootup

T1024 Second Core Bootup

Re: T1024 Second Core Bootup