topic Re: Custom T4080 design does not boot from NOR Flash in T-Series

Custom T4080 design does not boot from NOR Flash

chrisdeloach — Thu, 22 Feb 2018 16:21:45 GMT

I have a custom T4080 design that I have been using the BDI3000 to run U-boot from SRAM. The T4080 gets its RCW and PBI from an I2C eeprom. I have a NOR flash on IFC Chip Select 0 which I want to boot U-boot from. When I disconnect the BDI and let the processor boot normally I never see any Chip Selects on CS0 which is the BOOT_LOC in the RCW. I know that it gets all the way down the Reset and Initialization sequence to run PBI because I can see our IFC bus go from 50MHZ to 100MHZ which is set by the clock divider in the PBI. That leads me to believe we are getting to step 18 System Ready State. Unfortunately, I do not have the ASLEEP signal pulled over to our FPGA which pulls in all the other JTAG signals, so I cannot verify that portion. HRESET_B seems to be high and HRESET_REG_B does not seem to be low.

Does anyone have a suggestion on if I can still hook up the BDI and have it run the normal reset sequence of the T4080 instead of halting it, or any other signals I should be looking at?

Can the T4080 go to an Interrupt vector before the boot vector?

Re: Custom T4080 design does not boot from NOR Flash

ufedor — Fri, 23 Feb 2018 02:03:03 GMT

First - it is required to ensure (using a digital scope) that all notes after the Table 1. Pinout list by bus in the QorIQ T4160/T4080 Data Sheet are considered and fulfilled.

To investigate the issue further it is needed to inspect the processor connection schematics and RCW binary image programmed into the I2C EEPROM.

It is convenient to do that in a form of Technical Case:

How I could create a Service Request?

Re: Custom T4080 design does not boot from NOR Flash

chrisdeloach — Thu, 01 Mar 2018 17:29:54 GMT

I found that the PBI was overwriting what PBL setup for booting. The PBI had modified settings for IFC_CSPR0 and IFC_AMASK0 to make accesses to the NOR Flash work in the BDI and U-boot. I had to remove these register writes from the PBI so that the T4080 could set them as it needed to in the PBL. Having a different flash address in CSPR was probably causing and exception since only the top 4K is mapped in the default TLB.