T-SeriesのトピックSecond Core Start T2080 https://community.nxp.com/t5/T-Series/Second-Core-Start-T2080/m-p/765541#M2510 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>&nbsp;&nbsp;&nbsp;I am trying to start core 1 from core 0 after I have initialized all peripherals in my T2080 board. I first configure the boot space translation registers to translate the boot addressees, then I am setting the DCFG_CCSR_BRR bit 1 to 1 to enable the core, and ensuring that bit 1 in the&nbsp; DCFG_CCSR_COREDISR is 0 and none of my code is being executed. However, when I debug the two cores by connecting the TAP to the board and stepping through the ROM code on the board I do get output from core 1. It seems that even though I am enabling core 1 via the DCFG_CCSR_BRR bit it still isn't executing.&nbsp;</P></BODY></HTML> Wed, 21 Feb 2018 23:06:01 GMT stevenstarnes 2018-02-21T23:06:01Z Second Core Start T2080 https://community.nxp.com/t5/T-Series/Second-Core-Start-T2080/m-p/765541#M2510 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>&nbsp;&nbsp;&nbsp;I am trying to start core 1 from core 0 after I have initialized all peripherals in my T2080 board. I first configure the boot space translation registers to translate the boot addressees, then I am setting the DCFG_CCSR_BRR bit 1 to 1 to enable the core, and ensuring that bit 1 in the&nbsp; DCFG_CCSR_COREDISR is 0 and none of my code is being executed. However, when I debug the two cores by connecting the TAP to the board and stepping through the ROM code on the board I do get output from core 1. It seems that even though I am enabling core 1 via the DCFG_CCSR_BRR bit it still isn't executing.&nbsp;</P></BODY></HTML> Wed, 21 Feb 2018 23:06:01 GMT https://community.nxp.com/t5/T-Series/Second-Core-Start-T2080/m-p/765541#M2510 stevenstarnes 2018-02-21T23:06:01Z