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    <title>topic Re: T1024 NOR Flash CFG_RCW_SRC Setting in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757318#M2483</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Originally you wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; In the Reference Manual, page &lt;STRONG&gt;1084&lt;/STRONG&gt;, it says that address shift value is 5.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please consider that the RM example has been given as a generic example. Not specific to this SoC. Just to explain the concept. The RM has the following note:&lt;/P&gt;&lt;P&gt;"NOTE&lt;BR /&gt;These figures are intended to be examples only and may show ADDR pins that are not supported."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the specific case only IFC_A[16:27] are available for addressing purpose. In such case LSb of the system address will appear on A27. Shifting system address by 4 should work. ADM_SHFT should be 4.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; Is&amp;nbsp;there a way of booting CPU from NOR flash&amp;nbsp;using the connections on the Reference Manual, Figure 23-9.&lt;/P&gt;&lt;P&gt;No.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 17 May 2018 09:13:25 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2018-05-17T09:13:25Z</dc:date>
    <item>
      <title>T1024 NOR Flash CFG_RCW_SRC Setting</title>
      <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757315#M2480</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have a custom board that has T1024 and a 128 MB x16 NOR Flash. In the Reference Manual, page 1084, it says that address shift value is 5. However, in the cfg_rcw_src field there is no option such 5, only 4, 7, 10 shift values are available. What value should I select for the cfg_rcw_src field?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 May 2018 05:28:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757315#M2480</guid>
      <dc:creator>bltuna</dc:creator>
      <dc:date>2018-05-16T05:28:30Z</dc:date>
    </item>
    <item>
      <title>Re: T1024 NOR Flash CFG_RCW_SRC Setting</title>
      <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757316#M2481</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Which revision of the Manual is in question?&lt;/P&gt;&lt;P&gt;I do not see "5" in the Rev.0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is there an external address latch for the NOR Flash?&lt;/P&gt;&lt;P&gt;If "yes" - you can refer to the QorIQ T1024 Reference Design Board Quick Start (at &lt;A class="link-titled" href="https://www.nxp.com/support/developer-resources/software-development-tools/codewarrior-development-tools/run-control-devices/qoriq-t1024-reference-design-board:T1024RDB?tab=Documentation_Tab" title="https://www.nxp.com/support/developer-resources/software-development-tools/codewarrior-development-tools/run-control-devices/qoriq-t1024-reference-design-board:T1024RDB?tab=Documentation_Tab"&gt;QorIQ® T1024 Reference Design Board|NXP&lt;/A&gt;):&lt;/P&gt;&lt;P&gt;cfg_rcw_src&lt;/P&gt;&lt;P&gt;000100111: NOR boot mode&lt;/P&gt;&lt;P&gt;(shift 0)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 May 2018 14:08:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757316#M2481</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-05-16T14:08:21Z</dc:date>
    </item>
    <item>
      <title>Re: T1024 NOR Flash CFG_RCW_SRC Setting</title>
      <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757317#M2482</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It's stated in Rev. 0, page 1082&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="nor_shift.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/32555i88AD0CE1390F372C/image-size/large?v=v2&amp;amp;px=999" role="button" title="nor_shift.PNG" alt="nor_shift.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, we use external latch.&lt;/P&gt;&lt;P&gt;In the reference design IFC_A29 and IFC_30 pins are used as address bits, but we use these pins as IFC_RB2 and IFC_RB3, because we have devices more than two on the IFC bus. So, we followed the reference manual while designing our board. Is&amp;nbsp;there a way of booting CPU from NOR flash&amp;nbsp;using the connections on the Reference Manual, Figure 23-9.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="nor_connection.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/32864i2237D3C75B07BE1D/image-size/large?v=v2&amp;amp;px=999" role="button" title="nor_connection.PNG" alt="nor_connection.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 May 2018 06:11:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757317#M2482</guid>
      <dc:creator>bltuna</dc:creator>
      <dc:date>2018-05-17T06:11:55Z</dc:date>
    </item>
    <item>
      <title>Re: T1024 NOR Flash CFG_RCW_SRC Setting</title>
      <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757318#M2483</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Originally you wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; In the Reference Manual, page &lt;STRONG&gt;1084&lt;/STRONG&gt;, it says that address shift value is 5.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please consider that the RM example has been given as a generic example. Not specific to this SoC. Just to explain the concept. The RM has the following note:&lt;/P&gt;&lt;P&gt;"NOTE&lt;BR /&gt;These figures are intended to be examples only and may show ADDR pins that are not supported."&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the specific case only IFC_A[16:27] are available for addressing purpose. In such case LSb of the system address will appear on A27. Shifting system address by 4 should work. ADM_SHFT should be 4.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt; Is&amp;nbsp;there a way of booting CPU from NOR flash&amp;nbsp;using the connections on the Reference Manual, Figure 23-9.&lt;/P&gt;&lt;P&gt;No.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 May 2018 09:13:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757318#M2483</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-05-17T09:13:25Z</dc:date>
    </item>
    <item>
      <title>Re: T1024 NOR Flash CFG_RCW_SRC Setting</title>
      <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757319#M2484</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to your mesages and reference manual, I assume that the connections for a 128 MB x16 NOR Flash&amp;nbsp;should be like that&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="nor_con.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/33931i1318A4C1F8D86E8D/image-size/large?v=v2&amp;amp;px=999" role="button" title="nor_con.PNG" alt="nor_con.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is that right?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 May 2018 11:07:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757319#M2484</guid>
      <dc:creator>bltuna</dc:creator>
      <dc:date>2018-05-17T11:07:18Z</dc:date>
    </item>
    <item>
      <title>Re: T1024 NOR Flash CFG_RCW_SRC Setting</title>
      <link>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757320#M2485</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You are right.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 17 May 2018 15:42:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1024-NOR-Flash-CFG-RCW-SRC-Setting/m-p/757320#M2485</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-05-17T15:42:04Z</dc:date>
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