IFC controller INPUT CLOCK

faizmajeed — Tue, 28 Nov 2017 13:03:57 GMT

I am using T1042 and interfacing some Flashes to IFC. I am confused about its frequency that is coming from platform block. This can be min of 300MHZ. IFC will get 300/2 which is 150MHZ. But IFC supports 100MHZ. how should i solve this clocking problem.

I have attached some snaps to justify my question. please review these snaps and suggest me some solution.

Re: IFC controller INPUT CLOCK

r8070z — Tue, 28 Nov 2017 13:56:48 GMT

Have a great day,

The 100 MHz limit means that F_pmck/2/IFC_CCR[CLKDIV] must be less or equal to 100 MHz, where F_pmck is platform clock frequency. It does not mean that we can reach 100 MHz at any available platform clock frequency. For F_pmck = 300 MHz maximal IFC_CLK frequency is 300/2/2=75 MHz.

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T-Series中的主题 IFC controller INPUT CLOCK

IFC controller INPUT CLOCK

Re: IFC controller INPUT CLOCK