In T2080 Processor CS0 is asserting while trying to assert CS1

soumyasephalika — Sat, 18 Apr 2015 12:37:07 GMT

Dear All,

In my T2080 processor board. The CS0 has been connected to a NOR flash of 256MB & one more NOR flash of 256MB is connected to the same bus with CS1 chip select. While trying to read the second NOR flash(CS1) the CS0 is asserting. I have checked the memory mapping for CS0 & CS1.

Kindly suggest what will be the probable root cause for this error.

Regards

Soumya

Re: In T2080 Processor CS0 is asserting while trying to assert CS1

r8070z — Fri, 24 Apr 2015 08:37:57 GMT

Have a great day, my name Sergey

CSn (chip select n) selected if,

{BASE_ADDRn[0:7], (BASE_ADDRn[8:23] & AMn[0:15])} == {SYSTEM_ADDR[39:32], (SYSTEM_ADDR[31:16] & AMn[0:15])},

where

* SYSTEM_ADDR is a 40-bit incoming address from the system side. Index 39-32 represents 8 address msbs

* SYSTEM_ADDR[31:16] represent the next lower 16 address bits and the remain 16 lsbs are not used in the bank selection

* BASE_ADDRn[0:8] and BASE_ADDRn[8:23] is defined in the IFC_CSPRn_EXT and IFC_CSPRn.

* The address mask AMn[0:15] is defined in the IFC_AMASKn

1) HOWEVER after reset, until a first write transaction occurs to update AMASK0 register, all the transactions coming from the system side will always be mapped to CS0. After receiving the first write transaction to update AMASK0, the chip select decoding logic will work as per the above mentioned equation. Ensure that AMASK0 has been set after reset.

2) If you are sure that AMASK0 has been set then ensure that above mentioned equation does not provide overlapped regions for CS0 and CS1.

3) If the CS0 and CS1 region settings are not overlapped then ensure that software really uses address for CS1 region in your test.

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T-Series中的主题 In T2080 Processor CS0 is asserting while trying to assert CS1

In T2080 Processor CS0 is asserting while trying to assert CS1

Re: In T2080 Processor CS0 is asserting while trying to assert CS1