T1042 DDR Controller query!!

faizmajeed — Mon, 30 Oct 2017 13:01:06 GMT

Hi i am using T1042 processor and i am trying to interface SDRAM with DDR Memory Controller. The reference manual mentions that the memory controller is receiving a 40 bit address from "core master" that is being converted to a 16 bit address later on. Can anyone please elaborate what is a core master?

Re: T1042 DDR Controller query!!

r8070z — Tue, 31 Oct 2017 08:59:40 GMT

Have a great day,

Core master means any master which can access to the DDR memory, for instance DMA or e5500 core. Manual’s Figure 14-1. DDR Memory Controller Simplified Block Diagram shows that master is providing address for access. By the way the T1040 reference manual does not say directly that it is a 40-bit address. I guess the T1040 reference manual DDR controller description is based on the general DDR memory controller IP description which can support up to 40-bit master address. So they named the least significant master address bits as 35-39 in the leftmost column. The same address multiplexing tables we can see in the T2080 reference manual where really 40-bit physical address is supported. The T1042 supports 36-bit physical address. In any case the left column in the address multiplexing tables presents the least significant address bits. So for the T1042 we can say that '39' is name of the least significant while '5' is name the most significant bit of the T1042 36-bit physical address.

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T-Series中的主题 T1042 DDR Controller query!!

T1042 DDR Controller query!!

Re: T1042 DDR Controller query!!