topic Re: 64 bit DDR controller configuration using spd not bootup(UBOOT) in T-Series

64 bit DDR controller configuration using spd not bootup(UBOOT)

dhanasekaran — Fri, 22 Sep 2017 09:17:51 GMT

Hi!

we use T4240 processor with 4 GB( DDR3L) connected in DDRC1- Bus width 64bit , 2GB( DDR3L) connected in DDRC2 Bus width 32bit and DDRC3 don't have any DDR Ram. We configuring DDR ram by using spd Value in Uboot. . when DRRC1 as 64bit and DRRC2 as 32bit the U-boot hangs.But when configuration DRRC1 and DRRC2 as 32bit U-Boot works fine and mapped as 4GB. Any suggestion Please!

BOOTED UP fine log:

U-Boot 2016.012.0+ga9b437f (Jul 11 2017 - 11:48:39 +0530)

CPU0: T4240, Version: 2.0, (0x82400020)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1000 MHz, CPU1:1000 MHz, CPU2:1000 MHz, CPU3:1000 MHz,
       CPU4:1000 MHz, CPU5:1000 MHz, CPU6:1000 MHz, CPU7:1000 MHz,
       CPU8:1000 MHz, CPU9:1000 MHz, CPU10:1000 MHz, CPU11:1000 MHz,
       CCB:733.333 MHz,
       DDR:600 MHz (1200 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN: 366.667 MHz
       PME:   366.667 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
I2C:   ready
SPI:   ready
DRAM: Initializing....using SPD
intractive dhana
Detected UDIMM
Detected UDIMM
total 2 GB
total 2 GB
CONFIG_PPC
no interleaveing inside law
no interleaveing inside law
spl build 0    config ramboot 02 GiB left unmapped
4 GiB (DDR3, 32-bit, CL=9, ECC off)
VID: Could not find voltage regulator on I2C.
Warning: Adjusting core voltage failed.
Flash: ERROR: too many flash sectors
256 MiB
L2:    2 MiB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000
Corenet Platform Cache: 1 MiB enabled
Using SERDES1 Protocol: 27 (0x1b)
Using SERDES2 Protocol: 27 (0x1b)
Using SERDES3 Protocol: 1 (0x1)
Using SERDES4 Protocol: 9 (0x9)
NAND: 0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

PCIE Switch Initialize all portsPCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe260000
PCIe3: Bus 01 - 01
PCIe4: Root Complex, no link, regs @ 0xfe270000
PCIe4: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Net:   Invalid SerDes2 protocol for T4240RDB
Fman1: Uploading microcode version 108.4.5
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 1
Failed to connect
Could not get PHY for FSL_MDIO0: addr 2
Failed to connect
Could not get PHY for FSL_MDIO0: addr 3
Failed to connect
Fman2: Uploading microcode version 108.4.5
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
FM1@DTSEC1 [PRIME]
Error: FM1@DTSEC1 address not set.
, FM1@DTSEC2
Error: FM1@DTSEC2 address not set.
, FM1@DTSEC3
Error: FM1@DTSEC3 address not set.
, FM1@DTSEC4
Error: FM1@DTSEC4 address not set.
, FM1@DTSEC9
Error: FM1@DTSEC9 address not set.
, FM1@DTSEC10
Error: FM1@DTSEC10 address not set.
, FM2@DTSEC1
Error: FM2@DTSEC1 address not set.
, FM2@DTSEC2
Error: FM2@DTSEC2 address not set.
, FM2@DTSEC3
Error: FM2@DTSEC3 address not set.
, FM2@DTSEC4
Error: FM2@DTSEC4 address not set.
, FM2@DTSEC9
Error: FM2@DTSEC9 address not set.
, FM2@DTSEC10
Error: FM2@DTSEC10 address not set.

Hit any key to stop autoboot: 10

BOOT UP Fail log:

CPU0: T4240, Version: 2.0, (0x82400020)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1000 MHz, CPU1:1000 MHz, CPU2:1000 MHz, CPU3:1000 MHz,
       CPU4:1000 MHz, CPU5:1000 MHz, CPU6:1000 MHz, CPU7:1000 MHz,
       CPU8:1000 MHz, CPU9:1000 MHz, CPU10:1000 MHz, CPU11:1000 MHz,
       CCB:733.333 MHz,
       DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN: 366.667 MHz
       PME:   366.667 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 1606000f 0f0f0f0f 00000000 00000000
       00000010: 6c360848 007f4c00 1c026000 15000000
       00000020: 00080000 ee0000ee 00000000 000287fc
       00000030: 00000000 50000000 00000000 00000028
I2C:   ready
Board: T4240RDB, SERDES Reference Clocks:
       SERDES1=100MHz SERDES2=156.25MHz
       SERDES3=100MHz SERDES4=100MHz
SPI:   ready
DRAM: Initializing....using SPD
DDR Interactive
dimm ctrl no 0
dimm ctrl no 1
n_ranks 1
n_ranks 1
Detected UDIMM
Detected UDIMM
hwconfig has unrecognized parameter for ctlr_intlv.
hwconfig has unrecognized parameter for ctlr_intlv.
total 4 GB
total 2 GB
CONFIG_PPC
4 GiB left unmapped
6 GiB (DDR3, 64-bit, CL=11, ECC off)

Thanks regards!

dhanasekaran K

Re: 64 bit DDR controller configuration using spd not bootup(UBOOT)

Bulat — Mon, 25 Sep 2017 12:01:35 GMT

It looks like a problem with memory controller interleaving, it is not possible to interleave two controllers with different memory configuration. Try to disable interleaving with following line in u-boot:

setenv hwconfig "fsl_ddr:ctlr_intlv=null"

Regards,

Bulat

Re: 64 bit DDR controller configuration using spd not bootup(UBOOT)

dhanasekaran — Tue, 03 Oct 2017 08:54:57 GMT

Hi!

sorry for the Delay, we face some other issue on our board so, can't check ddr, Now we checks and modify HWCONFIG as you mentioned but it still now boot properly, please view the log

**************************************************************************************************************
=> printenv hwconfig
hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=auto;usb1:dr_mode=host,phy_type=utmi

******************************************************************************************************************

initcall: effa88ac

U-Boot 2016.012.0+ga9b437f (Sep 30 2017 - 12:18:26 -0400)

initcall: eff4e818
U-Boot code: EFF40000 -> F0000000 BSS: -> F0050AE0
initcall: eff4842c
CPU0: T4240, Version: 2.0, (0x82400020)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1000 MHz, CPU1:1000 MHz, CPU2:1000 MHz, CPU3:1000 MHz,
       CPU4:1000 MHz, CPU5:1000 MHz, CPU6:1000 MHz, CPU7:1000 MHz,
       CPU8:1000 MHz, CPU9:1000 MHz, CPU10:1000 MHz, CPU11:1000 MHz,
       CCB:733.333 MHz,
       DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN: 366.667 MHz
       PME:   366.667 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 1606000f 0f0f0f0f 00000000 00000000
       00000010: 6c361848 00774c00 1c026000 15000000
       00000020: 00080000 ee0000ee 00000000 000287fc
       00000030: 00000000 50000000 00000000 00000028
initcall: eff4e560
initcall: eff4e928
I2C:   Requested speed:100000, i2c_clk:366666663
FDR:0x34, div:5120, ga:0x4, gb:0x5, a:10, b:512, speed:71614
Tr <= 1249 ns
FDR:0x33, div:4096, ga:0x7, gb:0x4, a:16, b:256, speed:89518
Tr <= 550 ns
FDR:0x0f, div:3840, ga:0xb, gb:0x3, a:30, b:128, speed:95486
Tr <= 201 ns
divider:3666, est_div:3840, DFSR:18
FDR:0x0f, speed:95486
ready
initcall: eff4f220
Board: T4240RDB, SERDES Reference Clocks:
       SERDES1=100MHz SERDES2=156.25MHz
       SERDES3=100MHz SERDES4=100MHz
initcall: eff4e8e8
SPI:   ready
initcall: eff4e8b4
DRAM: initcall: eff4e858
Initializing....using SPD
DDR Interactive
FSL DDR>dddddd                  compute

starting at step 1 (STEP_GET_SPD)
Total no of controller 1
dimm ctrl no 0
dimm ctrl no 1
n_ranks 1
DDR: DDR III rank density = 0x        80000000
n_ranks 1
DDR: DDR III rank density = 0x        80000000
Computing lowest common DIMM parameters for memctl=0
Detected UDIMM
lowest_common_spd_caslat is 0xb
outpdimm->taamin_ps is 0x35b6
mclk_ps is 0x4e2
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps   = 13750
trp_ps    = 13750
tras_ps   = 35000
twtr_ps   = 7500
trfc_ps   = 350000
trrd_ps   = 7500
twr_ps    = 15000
trc_ps    = 48750
Computing lowest common DIMM parameters for memctl=1
Detected UDIMM
lowest_common_spd_caslat is 0xb
outpdimm->taamin_ps is 0x35b6
mclk_ps is 0x4e2
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps   = 13750
trp_ps    = 13750
tras_ps   = 35000
twtr_ps   = 7500
trfc_ps   = 350000
trrd_ps   = 7500
twr_ps    = 15000
trc_ps    = 48750
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
memory controller interleaving disabled.
Found timing match: n_ranks 1, data rate 1700, rank_gb 0
   clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x80a0a0c,
wrlvl_ctrl_3 0xc0d0e0a
Reloading memory controller configuration options for memctl=1
mclk_ps = 1250 ps
memory controller interleaving disabled.
Found timing match: n_ranks 1, data rate 1700, rank_gb 0
   clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x80a0a0c,
wrlvl_ctrl_3 0xc0d0e0a
0 of 2 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
dbw_cap_adj[1]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x80000000
ctrl 1 dimm 0 base 0x80000000
ctrl 1 total 0x80000000
Total mem by __step_assign_addresses is 0x100000000
Total mem 4294967296 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x0000007f
FSLDDR: cs[0]_config = 0x80044402
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01111000
FSLDDR: timing_cfg_1 = 0xbcb40c66
FSLDDR: timing_cfg_2 = 0x0040c160
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc70c0000
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x24401110
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x02800000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x080a0a0c
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
FSLDDR: cs[0]_bnds = 0x008000ff
FSLDDR: cs[0]_config = 0x80044402
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01111000
FSLDDR: timing_cfg_1 = 0xbcb40c66
FSLDDR: timing_cfg_2 = 0x0040c160
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc70c0000
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x24401110
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x02800000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x080a0a0c
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
FSL DDR>edit c0 d0 spd 8 0x03

FSL DDR>compute

starting at step 2 (STEP_COMPUTE_DIMM_PARMS)
Total no of controller 1
SPD checksum unexpected.
Checksum lsb in SPD = 64, computed SPD = 79
Checksum msb in SPD = 95, computed SPD = E5
DIMM 0: failed checksum
Error: compute_dimm_parameters non-zero returned FATAL value for memctl=0 dimm=0
FSL DDR>edit c0 d0 spd 126 0x79

FSL DDR>edit c0 d0 spd 127 0xe5

FSL DDR>compute

starting at step 2 (STEP_COMPUTE_DIMM_PARMS)
Total no of controller 1
n_ranks 1
DDR: DDR III rank density = 0x       100000000
n_ranks 1
DDR: DDR III rank density = 0x        80000000
Computing lowest common DIMM parameters for memctl=0
Detected UDIMM
lowest_common_spd_caslat is 0xb
outpdimm->taamin_ps is 0x35b6
mclk_ps is 0x4e2
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps   = 13750
trp_ps    = 13750
tras_ps   = 35000
twtr_ps   = 7500
trfc_ps   = 350000
trrd_ps   = 7500
twr_ps    = 15000
trc_ps    = 48750
Computing lowest common DIMM parameters for memctl=1
Detected UDIMM
lowest_common_spd_caslat is 0xb
outpdimm->taamin_ps is 0x35b6
mclk_ps is 0x4e2
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps   = 13750
trp_ps    = 13750
tras_ps   = 35000
twtr_ps   = 7500
trfc_ps   = 350000
trrd_ps   = 7500
twr_ps    = 15000
trc_ps    = 48750
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
memory controller interleaving disabled.
Found timing match: n_ranks 1, data rate 1700, rank_gb 0
   clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x80a0a0c,
wrlvl_ctrl_3 0xc0d0e0a
Reloading memory controller configuration options for memctl=1
mclk_ps = 1250 ps
memory controller interleaving disabled.
Found timing match: n_ranks 1, data rate 1700, rank_gb 0
   clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x80a0a0c,
wrlvl_ctrl_3 0xc0d0e0a
0 of 2 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
dbw_cap_adj[1]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x100000000
ctrl 1 dimm 0 base 0x100000000
ctrl 1 total 0x80000000
Total mem by __step_assign_addresses is 0x180000000
Total mem 6442450944 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x000000ff
FSLDDR: cs[0]_config = 0x80044402
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01111000
FSLDDR: timing_cfg_1 = 0xbcb40c66
FSLDDR: timing_cfg_2 = 0x0040c160
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc7040000
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x24401110
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x02800000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x080a0a0c
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
FSLDDR: cs[0]_bnds = 0x0100017f
FSLDDR: cs[0]_config = 0x80044402
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01111000
FSLDDR: timing_cfg_1 = 0xbcb40c66
FSLDDR: timing_cfg_2 = 0x0040c160
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc70c0000
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x24401110
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x02800000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x080a0a0c
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
FSL DDR>go

starting at step 2 (STEP_COMPUTE_DIMM_PARMS)
Total no of controller 1
n_ranks 1
DDR: DDR III rank density = 0x       100000000
n_ranks 1
DDR: DDR III rank density = 0x        80000000
Computing lowest common DIMM parameters for memctl=0
Detected UDIMM
lowest_common_spd_caslat is 0xb
outpdimm->taamin_ps is 0x35b6
mclk_ps is 0x4e2
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps   = 13750
trp_ps    = 13750
tras_ps   = 35000
twtr_ps   = 7500
trfc_ps   = 350000
trrd_ps   = 7500
twr_ps    = 15000
trc_ps    = 48750
Computing lowest common DIMM parameters for memctl=1
Detected UDIMM
lowest_common_spd_caslat is 0xb
outpdimm->taamin_ps is 0x35b6
mclk_ps is 0x4e2
Warning: not all DIMMs ECC capable, cant enable ECC
tCKmin_ps = 1250
trcd_ps   = 13750
trp_ps    = 13750
tras_ps   = 35000
twtr_ps   = 7500
trfc_ps   = 350000
trrd_ps   = 7500
twr_ps    = 15000
trc_ps    = 48750
Reloading memory controller configuration options for memctl=0
mclk_ps = 1250 ps
memory controller interleaving disabled.
Found timing match: n_ranks 1, data rate 1700, rank_gb 0
   clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x80a0a0c,
wrlvl_ctrl_3 0xc0d0e0a
Reloading memory controller configuration options for memctl=1
mclk_ps = 1250 ps
memory controller interleaving disabled.
Found timing match: n_ranks 1, data rate 1700, rank_gb 0
   clk_adjust 5, wrlvl_start 8, wrlvl_ctrl_2 0x80a0a0c,
wrlvl_ctrl_3 0xc0d0e0a
0 of 2 controllers are interleaving.
Checking interleaving options completed
dbw_cap_adj[0]=0
dbw_cap_adj[1]=0
ctrl 0 dimm 0 base 0x0
ctrl 0 total 0x100000000
ctrl 1 dimm 0 base 0x100000000
ctrl 1 total 0x80000000
Total mem by __step_assign_addresses is 0x180000000
Total mem 6442450944 assigned
FSL Memory ctrl register computation
FSLDDR: cs[0]_bnds = 0x000000ff
FSLDDR: cs[0]_config = 0x80044402
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01111000
FSLDDR: timing_cfg_1 = 0xbcb40c66
FSLDDR: timing_cfg_2 = 0x0040c160
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc7040000
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x24401110
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x02800000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x080a0a0c
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
FSLDDR: cs[0]_bnds = 0x0100017f
FSLDDR: cs[0]_config = 0x80044402
FSLDDR: cs[0]_config_2 = 0x00000000
FSLDDR: timing_cfg_0 = 0x5011010c
FSLDDR: timing_cfg_3 = 0x01111000
FSLDDR: timing_cfg_1 = 0xbcb40c66
FSLDDR: timing_cfg_2 = 0x0040c160
FSLDDR: ddr_cdr1 = 0x80040000
FSLDDR: ddr_cdr2 = 0x00000001
FSLDDR: ddr_sdram_cfg = 0xc70c0000
DDR: ddr_data_init = 0xdeadbeef
FSLDDR: ddr_sdram_cfg_2 = 0x24401110
FSLDDR: ddr_sdram_mode = 0x00441c70
FSLDDR: ddr_sdram_mode_3 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_5 = 0x00000000
FSLDDR: ddr_sdram_mode_2 = 0x00980000
FSLDDR: ddr_sdram_mode_4 = 0x00000000
FSLDDR: ddr_sdram_mode_6 = 0x00000000
FSLDDR: ddr_sdram_mode_8 = 0x00000000
FSLDDR: ddr_sdram_interval = 0x0c30030c
FSLDDR: clk_cntl = 0x02800000
FSLDDR: timing_cfg_4 = 0x00000001
FSLDDR: timing_cfg_5 = 0x04401400
FSLDDR: zq_cntl = 0x89080600
FSLDDR: wrlvl_cntl = 0x8675f608
FSLDDR: wrlvl_cntl_2 = 0x080a0a0c
FSLDDR: wrlvl_cntl_3 = 0x0c0d0e0a
end of memory = 6442450944
Programming controller 0
total 4 GB
Need to wait up to 66 * 10ms
Programming controller 1
total 2 GB
Need to wait up to 66 * 10ms
CONFIG_PPC
no interleaveing inside law
base 0
size 4294967296
ndimm_present 1
law_memctl 16
ctrl_num 0
setup ddr law base = 0x0, size 0x100000000, TRGT_ID 0x10
no interleaveing inside law
base 4294967296
size 2147483648
ndimm_present 1
law_memctl 17
ctrl_num 1
setup ddr law base = 0x100000000, size 0x80000000, TRGT_ID 0x11
total_memory by __fsl_ddr_sdram = 6442450944
4 GiB left unmapped
initcall: eff4ec18
Monitor len: 00110AE0
Ram size: 80000000
Ram top: 80000000
Reserving MP boot page to 7ffff000
initcall: eff4e5ac
initcall: eff4e5c0
initcall: eff4e79c
Reserving 1090k for U-Boot at: 7fee0000
initcall: eff4e74c
Reserving 4104k for malloc() at: 7fade000
initcall: eff4eb0c
Reserving 72 Bytes for Board Info at: 7faddfb8
initcall: eff4e5c8
initcall: eff4e6f8
Reserving 192 Bytes for Global Data at: 7faddef8
initcall: eff4e670
initcall: eff4e628
initcall: eff4ece8
initcall: eff4ebd8
initcall: eff4eb88
6 GiB (DDR3, 64-bit, CL=11, ECC off)
initcall: eff4e5d0
initcall: eff4e5fc
initcall: eff4e638
New Stack Pointer is: 7faddee0
initcall: eff4eaa8
initcall: eff4ea28
Relocation Offset is: 8ffa0000
Relocating to 7fee0000, new gd at 7faddef8, sp at 7faddee0
initcall: eff4e9e4

Thanks in Advance,

Regards ,

Dhanasekaran K.

Re: 64 bit DDR controller configuration using spd not bootup(UBOOT)

dhanasekaran — Thu, 12 Oct 2017 18:13:59 GMT

Hi!

What the configuration I have check to configure two DRRC without ECC and interleave in uboot and also in Codewarrior Tcl.

We check the above booted 32bit DDRC Values using codewarrior tap it not init properly that it sets memory region as zero and we cannot change it.(it always zero and provide machine check error during download)

Regards,

Dhanasekaran k

Re: 64 bit DDR controller configuration using spd not bootup(UBOOT)

dhanasekaran — Thu, 24 Jan 2019 01:29:16 GMT

It is solved by adjusting write leveling and chip select bound address parameters using code Warrier QCVS Tool.

Thanks.