<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: T4240 memory controller stuck when configure as 64bit  in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706480#M2188</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Bulat&lt;/P&gt;&lt;P&gt;It is solved by adjusting write leveling parameters using code Warrier QCVS Tool.&lt;/P&gt;&lt;P&gt;Thanks for the reply.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 24 Jan 2019 01:19:36 GMT</pubDate>
    <dc:creator>dhanasekaran</dc:creator>
    <dc:date>2019-01-24T01:19:36Z</dc:date>
    <item>
      <title>T4240 memory controller stuck when configure as 64bit</title>
      <link>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706478#M2186</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi everyone!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In out custom board we use T4240 with 6GB of Discrete dram which connected with DDR controllers as 4GB(DDRC1) and 2GB(DDRC2). By using SPD values I init Dram as 64bit DDRC1 and 32 bit for DDRC2. I get stuck in Uboot but when I changed it to 32bit for both DDRC it work so only 4GB of memory only detected out of 6GB.&amp;nbsp;&lt;/P&gt;&lt;P&gt;My configuration for 800mhz&amp;nbsp; &amp;nbsp;ddr clock&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;# DDR1 Controller Setup&lt;BR /&gt; # DDR1_DDR_SDRAM_CFG&lt;BR /&gt; mem [CCSR_ADDR 0x8110] = 0x67040000&lt;BR /&gt; # DDR1_CS0_BNDS&lt;BR /&gt; mem [CCSR_ADDR 0x8000] = 0x0000007f&lt;BR /&gt; # DDR1_CS1_BNDS&lt;BR /&gt; mem [CCSR_ADDR 0x8008] = 0x00000000&lt;BR /&gt; # DDR1_CS2_CONFIG&lt;BR /&gt; # mem [CCSR_ADDR 0x8088] = 0xffffffff&lt;BR /&gt; # DDR1_CS3_BNDS&lt;BR /&gt; # mem [CCSR_ADDR 0x808C] = 0xffffffff&lt;BR /&gt; # DDR1_CS0_CONFIG&lt;BR /&gt; mem [CCSR_ADDR 0x8080] = 0x80044402&lt;BR /&gt; # DDR1_CS1_CONFIG&lt;BR /&gt; mem [CCSR_ADDR 0x8084] = 0x00000000&lt;BR /&gt; # DDR1_CS0_CONFIG_2&lt;BR /&gt; mem [CCSR_ADDR 0x80C0] = 0x00000000&lt;BR /&gt; # DDR1_TIMING_CFG_0&lt;BR /&gt; mem [CCSR_ADDR 0x8104] = 0x5011010C&lt;BR /&gt; # DDR1_TIMING_CFG_1&lt;BR /&gt; mem [CCSR_ADDR 0x8108] = 0xBCB40C66&lt;BR /&gt; # DDR1_TIMING_CFG_2&lt;BR /&gt; mem [CCSR_ADDR 0x810C] = 0x0040C160&lt;BR /&gt; # DDR1_TIMING_CFG_3&lt;BR /&gt; mem [CCSR_ADDR 0x8100] = 0x01111000&lt;BR /&gt; # DDR1_DDR_SDRAM_CFG_2&lt;BR /&gt; mem [CCSR_ADDR 0x8114] = 0x24401110&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE&lt;BR /&gt; mem [CCSR_ADDR 0x8118] = 0x00441C70&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_2&lt;BR /&gt; mem [CCSR_ADDR 0x811C] = 0x00980000&lt;BR /&gt; # DDR1_DDR_SDRAM_INTERVAL&lt;BR /&gt; mem [CCSR_ADDR 0x8124] = 0x0C30030C&lt;BR /&gt; # DDR1_DDR_DATA_INIT&lt;BR /&gt; mem [CCSR_ADDR 0x8128] = 0xDEADBEEF&lt;BR /&gt; # DDR1_DDR_SDRAM_CLK_CNTL&lt;BR /&gt; mem [CCSR_ADDR 0x8130] = 0x02800000&lt;BR /&gt; # DDR1_DDR_INIT_ADDR&lt;BR /&gt; mem [CCSR_ADDR 0x8148] = 0x00000000&lt;BR /&gt; # DDR1_DDR_INIT_EXT_ADDRESS&lt;BR /&gt; mem [CCSR_ADDR 0x814C] = 0x00000000&lt;BR /&gt; # DDR1_TIMING_CFG_4&lt;BR /&gt; mem [CCSR_ADDR 0x8160] = 0x00000001&lt;BR /&gt; # DDR1_TIMING_CFG_5&lt;BR /&gt; mem [CCSR_ADDR 0x8164] = 0x04401400&lt;BR /&gt; # DDR1_DDR_ZQ_CNTL&lt;BR /&gt; mem [CCSR_ADDR 0x8170] = 0x89080600&lt;BR /&gt; # DDR1_DDR_WRLVL_CNTL&lt;BR /&gt; mem [CCSR_ADDR 0x8174] = 0x8675F608&lt;BR /&gt; # DDR1_DDR_WRLVL_CNTL_2&lt;BR /&gt; mem [CCSR_ADDR 0x8190] = 0x080A0A0C&lt;BR /&gt; # DDR1_DDR_WRLVL_CNTL_3&lt;BR /&gt; mem [CCSR_ADDR 0x8194] = 0x0C0D0E0A&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_3&lt;BR /&gt; mem [CCSR_ADDR 0x8200] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_4&lt;BR /&gt; mem [CCSR_ADDR 0x8204] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_5&lt;BR /&gt; mem [CCSR_ADDR 0x8208] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_6&lt;BR /&gt; mem [CCSR_ADDR 0x820C] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_7&lt;BR /&gt; mem [CCSR_ADDR 0x8210] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_8&lt;BR /&gt; mem [CCSR_ADDR 0x8214] = 0x00000000&lt;BR /&gt; # DDR1_DDRDSR_1&lt;BR /&gt; mem [CCSR_ADDR 0x8B20] = 0x00008080&lt;BR /&gt; # DDR1_DDRDSR_2&lt;BR /&gt; mem [CCSR_ADDR 0x8B24] = 0x80000000&lt;BR /&gt; # DDR1_DDRCDR_1&lt;BR /&gt; mem [CCSR_ADDR 0x8B28] = 0x80040000&lt;BR /&gt; # DDR1_DDRCDR_2&lt;BR /&gt; mem [CCSR_ADDR 0x8B2C] = 0x00000001&lt;BR /&gt; # DDR1_ERR_DISABLE - DISABLE&lt;BR /&gt; mem [CCSR_ADDR 0x8E44] = 0x00000000&lt;BR /&gt; # DDR1_ERR_SBE&lt;BR /&gt; mem [CCSR_ADDR 0x8E58] = 0x00000000&lt;/P&gt;&lt;P&gt;# DDR2 Controller Setup&lt;BR /&gt; # DDR2_DDR_SDRAM_CFG&lt;BR /&gt; mem [CCSR_ADDR 0x9110] = 0x67040000&lt;BR /&gt; # DDR1_CS0_BNDS&lt;BR /&gt; mem [CCSR_ADDR 0x9000] = 0x008000FF&lt;BR /&gt; # DDR1_CS1_BNDS&lt;BR /&gt; mem [CCSR_ADDR 0x9008] = 0x00000000&lt;BR /&gt; # DDR1_CS2_CONFIG&lt;BR /&gt; # mem [CCSR_ADDR 0x9088] = 0xffffffff&lt;BR /&gt; # DDR1_CS3_BNDS&lt;BR /&gt; # mem [CCSR_ADDR 0x908C] = 0xffffffff&lt;BR /&gt; # DDR1_CS0_CONFIG&lt;BR /&gt; mem [CCSR_ADDR 0x9080] = 0x80044402&lt;BR /&gt; # DDR1_CS1_CONFIG&lt;BR /&gt; mem [CCSR_ADDR 0x9084] = 0x00000000&lt;BR /&gt; # DDR1_CS0_CONFIG_2&lt;BR /&gt; mem [CCSR_ADDR 0x90C0] = 0x00000000&lt;BR /&gt; # DDR1_TIMING_CFG_0&lt;BR /&gt; mem [CCSR_ADDR 0x9104] = 0x5011010C&lt;BR /&gt; # DDR1_TIMING_CFG_1&lt;BR /&gt; mem [CCSR_ADDR 0x9108] = 0xBCB40C66&lt;BR /&gt; # DDR1_TIMING_CFG_2&lt;BR /&gt; mem [CCSR_ADDR 0x910C] = 0x0040C160&lt;BR /&gt; # DDR1_TIMING_CFG_3&lt;BR /&gt; mem [CCSR_ADDR 0x9100] = 0x01111000&lt;BR /&gt; # DDR1_DDR_SDRAM_CFG_2&lt;BR /&gt; mem [CCSR_ADDR 0x9114] = 0x24401110&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE&lt;BR /&gt; mem [CCSR_ADDR 0x9118] = 0x00441C70&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_2&lt;BR /&gt; mem [CCSR_ADDR 0x911C] = 0x00980000&lt;BR /&gt; # DDR1_DDR_SDRAM_INTERVAL&lt;BR /&gt; mem [CCSR_ADDR 0x9124] = 0x0C30030C&lt;BR /&gt; # DDR1_DDR_DATA_INIT&lt;BR /&gt; mem [CCSR_ADDR 0x9128] = 0xDEADBEEF&lt;BR /&gt; # DDR1_DDR_SDRAM_CLK_CNTL&lt;BR /&gt; mem [CCSR_ADDR 0x9130] = 0x02800000&lt;BR /&gt; # DDR1_DDR_INIT_ADDR&lt;BR /&gt; mem [CCSR_ADDR 0x9148] = 0x00000000&lt;BR /&gt; # DDR1_DDR_INIT_EXT_ADDRESS&lt;BR /&gt; mem [CCSR_ADDR 0x914C] = 0x00000000&lt;BR /&gt; # DDR1_TIMING_CFG_4&lt;BR /&gt; mem [CCSR_ADDR 0x9160] = 0x00000001&lt;BR /&gt; # DDR1_TIMING_CFG_5&lt;BR /&gt; mem [CCSR_ADDR 0x9164] = 0x04401400&lt;BR /&gt; # DDR1_DDR_ZQ_CNTL&lt;BR /&gt; mem [CCSR_ADDR 0x9170] = 0x89080600&lt;BR /&gt; # DDR1_DDR_WRLVL_CNTL&lt;BR /&gt; mem [CCSR_ADDR 0x9174] = 0x8675F608&lt;BR /&gt; # DDR1_DDR_WRLVL_CNTL_2&lt;BR /&gt; mem [CCSR_ADDR 0x9190] = 0x080A0A0C&lt;BR /&gt; # DDR1_DDR_WRLVL_CNTL_3&lt;BR /&gt; mem [CCSR_ADDR 0x9194] = 0x0C0D0E0A&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_3&lt;BR /&gt; mem [CCSR_ADDR 0x9200] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_4&lt;BR /&gt; mem [CCSR_ADDR 0x9204] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_5&lt;BR /&gt; mem [CCSR_ADDR 0x9208] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_6&lt;BR /&gt; mem [CCSR_ADDR 0x920C] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_7&lt;BR /&gt; mem [CCSR_ADDR 0x9210] = 0x00000000&lt;BR /&gt; # DDR1_DDR_SDRAM_MODE_8&lt;BR /&gt; mem [CCSR_ADDR 0x9214] = 0x00000000&lt;BR /&gt; # DDR1_DDRDSR_1&lt;BR /&gt; mem [CCSR_ADDR 0x9B20] = 0x00008080&lt;BR /&gt; # DDR1_DDRDSR_2&lt;BR /&gt; mem [CCSR_ADDR 0x9B24] = 0x80000000&lt;BR /&gt; # DDR1_DDRCDR_1&lt;BR /&gt; mem [CCSR_ADDR 0x9B28] = 0x80040000&lt;BR /&gt; # DDR1_DDRCDR_2&lt;BR /&gt; mem [CCSR_ADDR 0x9B2C] = 0x00000001&lt;BR /&gt; # DDR1_ERR_DISABLE - DISABLE&lt;BR /&gt; mem [CCSR_ADDR 0x9E44] = 0x00000000&lt;BR /&gt; # DDR1_ERR_SBE&lt;BR /&gt; mem [CCSR_ADDR 0x9E58] = 0x00000000&lt;BR /&gt; &lt;BR /&gt; # DDR3 Controller Setup&lt;BR /&gt; # DDR3_DDR_SDRAM_CFG&lt;BR /&gt; #mem [CCSR_ADDR 0xA110] = 0x67040000&lt;BR /&gt; # DDR3_CS0_BNDS&lt;BR /&gt; #mem [CCSR_ADDR 0xA000] = 0x0000017f&lt;BR /&gt; # DDR3_CS1_BNDS&lt;BR /&gt; #mem [CCSR_ADDR 0xA008] = 0x0000017f&lt;BR /&gt; # DDR3_CS2_CONFIG&lt;BR /&gt; # mem [CCSR_ADDR 0xA088] = 0xffffffff&lt;BR /&gt; # DDR3_CS3_BNDS&lt;BR /&gt; # mem [CCSR_ADDR 0xA08C] = 0xffffffff&lt;BR /&gt; # DDR3_CS0_CONFIG&lt;BR /&gt; #mem [CCSR_ADDR 0xA080] = 0x80044302&lt;BR /&gt; # DDR3_CS1_CONFIG&lt;BR /&gt; #mem [CCSR_ADDR 0xA084] = 0x80004302&lt;BR /&gt; # DDR3_CS0_CONFIG_2&lt;BR /&gt; mem [CCSR_ADDR 0xA0C0] = 0x00000000&lt;BR /&gt; # DDR3_TIMING_CFG_0&lt;BR /&gt; #mem [CCSR_ADDR 0xA104] = 0x90110004&lt;BR /&gt; # DDR3_TIMING_CFG_1&lt;BR /&gt; #mem [CCSR_ADDR 0xA108] = 0xdfd9ee57&lt;BR /&gt; # DDR3_TIMING_CFG_2&lt;BR /&gt; #mem [CCSR_ADDR 0xA10C] = 0x0048e8d8&lt;BR /&gt; # DDR3_TIMING_CFG_3&lt;BR /&gt; #mem [CCSR_ADDR 0xA100] = 0x01081000&lt;BR /&gt; # DDR3_DDR_SDRAM_CFG_2&lt;BR /&gt; #mem [CCSR_ADDR 0xA114] = 0x00401010&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE&lt;BR /&gt; #mem [CCSR_ADDR 0xA118] = 0x40441014&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_2&lt;BR /&gt; #mem [CCSR_ADDR 0xA11C] = 0x00a00000&lt;BR /&gt; # DDR3_DDR_SDRAM_INTERVAL&lt;BR /&gt; #mem [CCSR_ADDR 0xA124] = 0x0e38038e &lt;BR /&gt; # DDR3_DDR_DATA_INIT&lt;BR /&gt; #mem [CCSR_ADDR 0xA128] = 0xDEADBEEF&lt;BR /&gt; # DDR3_DDR_SDRAM_CLK_CNTL&lt;BR /&gt; #mem [CCSR_ADDR 0xA130] = 0x02000000&lt;BR /&gt; # DDR3_DDR_INIT_ADDR&lt;BR /&gt; #mem [CCSR_ADDR 0xA148] = 0x00000000&lt;BR /&gt; # DDR3_DDR_INIT_EXT_ADDRESS&lt;BR /&gt; #mem [CCSR_ADDR 0xA14C] = 0x00000000&lt;BR /&gt; # DDR3_TIMING_CFG_4&lt;BR /&gt; #mem [CCSR_ADDR 0xA160] = 0x00000001&lt;BR /&gt; # DDR3_TIMING_CFG_5&lt;BR /&gt; #mem [CCSR_ADDR 0xA164] = 0x05401400&lt;BR /&gt; # DDR3_DDR_ZQ_CNTL&lt;BR /&gt; #mem [CCSR_ADDR 0xA170] = 0x89080600&lt;BR /&gt; # DDR3_DDR_WRLVL_CNTL&lt;BR /&gt; #mem [CCSR_ADDR 0xA174] = 0x8675f609&lt;BR /&gt; # DDR3_DDR_WRLVL_CNTL_2&lt;BR /&gt; #mem [CCSR_ADDR 0xA190] = 0x090a0b0e&lt;BR /&gt; # DDR3_DDR_WRLVL_CNTL_3&lt;BR /&gt; #mem [CCSR_ADDR 0xA194] = 0x0f11120c&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_3&lt;BR /&gt; #mem [CCSR_ADDR 0xA200] = 0x00001014&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_4&lt;BR /&gt; #mem [CCSR_ADDR 0xA204] = 0x00a00000&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_5&lt;BR /&gt; #mem [CCSR_ADDR 0xA208] = 0x00001014&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_6&lt;BR /&gt; #mem [CCSR_ADDR 0xA20C] = 0x00a00000&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_7&lt;BR /&gt; #mem [CCSR_ADDR 0xA210] = 0x00001014&lt;BR /&gt; # DDR3_DDR_SDRAM_MODE_8&lt;BR /&gt; #mem [CCSR_ADDR 0xA214] = 0x00a00000&lt;BR /&gt; # DDR3_DDRDSR_1&lt;BR /&gt; #mem [CCSR_ADDR 0xAB20] = 0x00008080&lt;BR /&gt; # DDR3_DDRDSR_2&lt;BR /&gt; #mem [CCSR_ADDR 0xAB24] = 0x80000000&lt;BR /&gt; # DDR3_DDRCDR_1&lt;BR /&gt; #mem [CCSR_ADDR 0xAB28] = 0x80040000&lt;BR /&gt; # DDR3_DDRCDR_2&lt;BR /&gt; #mem [CCSR_ADDR 0xAB2C] = 0x00000001&lt;BR /&gt; # DDR3_ERR_DISABLE - DISABLE&lt;BR /&gt; #mem [CCSR_ADDR 0xAE44] = 0x00000000&lt;BR /&gt; # DDR3_ERR_SBE&lt;BR /&gt; #mem [CCSR_ADDR 0xAE58] = 0x00000000&lt;/P&gt;&lt;P&gt;wait 100&lt;BR /&gt; # DDR1_DDR_SDRAM_CFG&lt;BR /&gt; mem [CCSR_ADDR 0x8110] = 0xC70C0000&lt;BR /&gt; # DDR2_DDR_SDRAM_CFG&lt;BR /&gt; mem [CCSR_ADDR 0x9110] = 0xC70C0000&lt;BR /&gt; # DDR3_DDR_SDRAM_CFG&lt;BR /&gt; #mem [CCSR_ADDR 0xa110] = 0x67040000&lt;BR /&gt; wait 1000 &lt;BR /&gt; # DDR1_ERR_DISABLE - ENABLE&lt;BR /&gt; mem [CCSR_ADDR 0x8E44] = 0x00000000&lt;BR /&gt; # DDR2_ERR_DISABLE - ENABLE&lt;BR /&gt; mem [CCSR_ADDR 0x9E44] = 0x00000000&lt;BR /&gt; # DDR3_ERR_DISABLE - ENABLE&lt;BR /&gt; #mem [CCSR_ADDR 0xaE44] = 0x00000000&lt;/P&gt;&lt;P&gt;# CCF_MCINTLV3R - enable 3-way interleaving&lt;BR /&gt; # CCF_MCINTLV3R[27–31]: GRANULE_SIZE&lt;BR /&gt; # 01010 1 KB granule size&lt;BR /&gt; # 01100 4 KB granule size&lt;BR /&gt; # 01101 8 KB granule size&lt;BR /&gt; #mem [CCSR_ADDR 0x18004] = 0x800000[format %02x [format %.0f [expr 10 + [logToBaseTwo $GRANULE_SIZE]]]]&lt;BR /&gt; mem [CCSR_ADDR 0x18004] = 0xc&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regard,&lt;/P&gt;&lt;P&gt;dhanasekaran k&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 14 Oct 2017 09:24:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706478#M2186</guid>
      <dc:creator>dhanasekaran</dc:creator>
      <dc:date>2017-10-14T09:24:56Z</dc:date>
    </item>
    <item>
      <title>Re: T4240 memory controller stuck when configure as 64bit</title>
      <link>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706479#M2187</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Did you try to enable single 64-bit DDRC1? Does it work?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Oct 2017 03:42:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706479#M2187</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2017-10-24T03:42:50Z</dc:date>
    </item>
    <item>
      <title>Re: T4240 memory controller stuck when configure as 64bit</title>
      <link>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706480#M2188</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Bulat&lt;/P&gt;&lt;P&gt;It is solved by adjusting write leveling parameters using code Warrier QCVS Tool.&lt;/P&gt;&lt;P&gt;Thanks for the reply.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 24 Jan 2019 01:19:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T4240-memory-controller-stuck-when-configure-as-64bit/m-p/706480#M2188</guid>
      <dc:creator>dhanasekaran</dc:creator>
      <dc:date>2019-01-24T01:19:36Z</dc:date>
    </item>
  </channel>
</rss>

