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    <title>topic Re: t1040 ddr4  about odt question in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691279#M2147</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Missing MODT0 in the table is a typo.&lt;/P&gt;&lt;P&gt;For the discrete DDR4 SDRAM design please refer to the T1023RDB-PC schematics in the design files:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://cache.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip?fsrch=1&amp;amp;sr=4&amp;amp;pageNum=1" title="http://cache.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip?fsrch=1&amp;amp;sr=4&amp;amp;pageNum=1"&gt;http://cache.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip?fsrch=1&amp;amp;sr=4&amp;amp;pageNum=1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 02 Aug 2017 06:40:33 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2017-08-02T06:40:33Z</dc:date>
    <item>
      <title>t1040 ddr4  about odt question</title>
      <link>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691278#M2146</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In t1040 reference manual chapter 14&amp;nbsp;Table 14-3. Memory Address Signal Mappings for DDR4 &amp;nbsp; ，It list modt1 to odt1 &amp;nbsp;no introduce modt0 to odt0 &amp;nbsp; 。 &amp;nbsp;if I USE DDR4 CLK0 &amp;nbsp;and cke0 to design(no dimm)，zhe odt &amp;nbsp;used odt 0 ? I think &amp;nbsp;the table have&amp;nbsp;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 13px;"&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;different&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;EM class="" style="color: #333333; background-color: #ffffff; font-size: 13px;"&gt;interpretations&lt;/EM&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 02:51:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691278#M2146</guid>
      <dc:creator>于立冬</dc:creator>
      <dc:date>2017-08-02T02:51:55Z</dc:date>
    </item>
    <item>
      <title>Re: t1040 ddr4  about odt question</title>
      <link>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691279#M2147</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Missing MODT0 in the table is a typo.&lt;/P&gt;&lt;P&gt;For the discrete DDR4 SDRAM design please refer to the T1023RDB-PC schematics in the design files:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://cache.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip?fsrch=1&amp;amp;sr=4&amp;amp;pageNum=1" title="http://cache.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip?fsrch=1&amp;amp;sr=4&amp;amp;pageNum=1"&gt;http://cache.nxp.com/downloads/en/printed-circuit-boards/T1023RDB-PC-DS.zip?fsrch=1&amp;amp;sr=4&amp;amp;pageNum=1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 06:40:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691279#M2147</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-08-02T06:40:33Z</dc:date>
    </item>
    <item>
      <title>Re: t1040 ddr4  about odt question</title>
      <link>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691280#M2148</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;T1023 &amp;nbsp;RDB &amp;nbsp;is ddr4 x8 * 4 =32bit &amp;nbsp;it have two cke &amp;nbsp;odt，if I want to use ddr4 X16(it have only &amp;nbsp;one &amp;nbsp;odt &amp;nbsp;cke) &amp;nbsp;I must use cke0 odt0 &amp;nbsp;not cke 1,odt 1 when use clk0?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 07:18:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691280#M2148</guid>
      <dc:creator>于立冬</dc:creator>
      <dc:date>2017-08-02T07:18:50Z</dc:date>
    </item>
    <item>
      <title>Re: t1040 ddr4  about odt question</title>
      <link>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691281#M2149</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please refer to the T1040 Family Design Checklist, Rev. 1:&lt;/P&gt;&lt;P&gt;"For a single, dual-ranked DIMM, consider the following connections&lt;/P&gt;&lt;P&gt;• MODT(0), MCS(0), MCKE(0)&lt;BR /&gt;• MODT(1), MCS(1), MCKE(1)"&lt;/P&gt;&lt;P&gt;So for a single rank you have to use MODT(0), MCS(0), MCKE(0).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 10:16:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/t1040-ddr4-about-odt-question/m-p/691281#M2149</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-08-02T10:16:29Z</dc:date>
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