T-SeriesのトピックT2080 discrete DDR3 configuration.

T2080 discrete DDR3 configuration.

vidyasagartata — Mon, 15 May 2017 14:28:14 GMT

Dear All,

Problem : We are using discrete DDR3 on chip, why "DRAM: Initializing....using SPD".

I have done #undef CONFIG_DDR_SPD and written QCVS DDR3 generated parameter in config file.

Please check and verify attached t208xrdb.h config file.

Any other configuration is required to configure

U-Boot 2016.01 (May 15 2017 - 09:02:14 +0530)

CPU0: T2080E, Version: 1.1, (0x85380011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:533.280 MHz, CPU1:533.280 MHz, CPU2:533.280 MHz, CPU3:533.280 MHz,
       CCB:533.280 MHz,
       DDR:933.310 MHz (1866.620 MT/s data rate) (Asynchronous), IFC:133.320 MHz
       FMAN1: 133.320 MHz
       QMAN: 266.640 MHz
       PME:   533.280 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 10070008 08000000 00000000 00000000
       00000010: 6c290002 70004200 fc027000 81000000
       00000020: 00800000 00000000 00000000 000323fc
       00000030: 00000000 00800009 00000000 00000004
I2C:   ready
Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NOR vBank0
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=125.00MHz
SD2_CLK1=125.00MHz, SD2_CLK2=125.00MHz
SPI:   ready
DRAM: Initializing....using SPD
16 MiB (DDR not enabled)

Thanks,

Sagar

Original Attachment has been moved to: T208xRDB.h.zip

Re: T2080 discrete DDR3 configuration.

yipingwang — Wed, 17 May 2017 13:44:37 GMT

Hello Vidya Sagar,

You also need to modify the file board/freescale/t208xrdb/ddr.c, the function fsl_ddr_sdram or fsl_ddr_sdram_size uses reading parameters from SPD method, please refer to drivers/ddr/fsl/main.c.

You could refer to the file board/freescale/p1010rdb/ddr.c for how to use the fixed SDRAM configuration parameter to initialize DDR controller.

Have a great day,
TIC

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Re: T2080 discrete DDR3 configuration.

vidyasagartata — Thu, 18 May 2017 13:43:53 GMT

Dear Yiping,

I have modified the uboot file according to p1010rdb, still same status,please find the modified files in the attachment and verify me if wrong.

We are using Chip select #0 and total DDR memory is 4GB.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Tue, 23 May 2017 10:56:21 GMT

Dear Yiping,

After modification getting below log:

DDR data rate configured 1066 in the RCW and QCVS DDR tool but getting "Waiting for D_INIT timeout. Memory may not work." and gets hang.

U-Boot 2016.01 (May 23 2017 - 15:46:05 +0530)

CPU0: T2080E, Version: 1.1, (0x85380011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:533.280 MHz, CPU1:533.280 MHz, CPU2:533.280 MHz, CPU3:533.280 MHz,
       CCB:533.280 MHz,
       DDR:533.320 MHz (1066.640 MT/s data rate) (Asynchronous), IFC:133.320 MHz
       FMAN1: 266.640 MHz
       QMAN: 266.640 MHz
       PME:   533.280 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 10040008 08000000 00000000 00000000
       00000010: 6c290002 70004200 fc027000 41000000
       00000020: 00800000 00000000 00000000 000323fc
       00000030: 00000100 00800009 00000000 00000004
I2C:   ready
Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NOR vBank1
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=125.00MHz
SD2_CLK1=125.00MHz, SD2_CLK2=125.00MHz
SPI:   ready
DRAM: Initializing....Configuring DDR for 1066.640 MT/s data rate
Waiting for D_INIT timeout. Memory may not work.

Please let me know what else need to configured.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

yipingwang — Thu, 01 Jun 2017 03:23:03 GMT

Hello Vidya,

I checked your attachment, I didn't find fixed SDRAM configuration parameters were used in your source code.

Please refer to board/freescale/p1010rdb/ddr.c about how to define fsl_ddr_cfg_regs_t structure to use these fixed SDRAM configuration parameters in ddr.c file.

Have a great day,
TIC

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Thu, 01 Jun 2017 14:25:08 GMT

Dear Yiping,

Thanks for reply.

We got 2 GB DDR3 working in our card, we are validating upto 4GB DDR, since board is having 4GB DDR memory.

Ethernet is working in u-boot also, trying to load kernel but getting crash, below is the log:

Please suggest solution, attached full log.

Linux version 4.1.8-rt8+gbd51baf (imx@imx-laptop) (gcc version 4.9.2 (GCC) ) #26 SMP Tue Apr 18 11:45:57 IST 2017

CoreNet Generic board

Zone ranges:

DMA

DMA32 empty

Normal empty

Movable zone start for each node

Early memory node ranges

node 0:

Initmem setup node 0

MMU: Allocated 2112 bytes of context maps for 255 contexts

PERCPU: Embedded 16 pages/cpu @c00000007fd00000 s28568 r0 d36968 u131072

Built 1 zonelists in Zone order, mobility grouping on. Total pages: 517120

Kernel command line: root=/dev/ram rw console=ttyS0,115200

log_buf_len individual max cpu contribution: 4096 bytes

log_buf_len total cpu_extra contributions: 28672 bytes

log_buf_len min size: 16384 bytes

log_buf_len: 65536 bytes

early log buf free: 12200(74%)

PID hash table entries: 4096 (order: 3, 32768 bytes)

Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)

Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)

Sorting __ex_table...

Memory: 1868372K/2097152K available (8612K kernel code, 1212K rwdata, 3196K rodata, 360K init, 798K bss, 228780K reserved, 0K cma-reserved)

Hierarchical RCU implementation.

RCU debugfs-based tracing is enabled.

CONFIG_RCU_FANOUT set to non-default value of 32

Additional per-CPU info printed with stalls.

RCU restricting CPUs from NR_CPUS=24 to nr_cpu_ids=8.

RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

NR_IRQS:512 nr_irqs:512 16

Unable to handle kernel paging request for data at address 0xc000000872fe94c8

Faulting instruction address: 0xc00000000085d234

Oops: Kernel access of bad area, sig: 11

SMP NR_CPUS=24 CoreNet Generic

Modules linked in:

CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.8-rt8+gbd51baf #26

task: c000000000c33340 ti: c000000000d08000 task.ti: c000000000d08000

NIP: c00000000085d234 LR: c00000000085d22c CTR: 0000000000000000

REGS: c000000000d0ba00 TRAP: 0300 Not tainted (4.1.8-rt8+gbd51baf)

MSR: 0000000080021000 <CE,ME> CR: 84022022 XER: 00000000

DEAR: c000000872fe94c8 ESR: 0000000000800000 SOFTE: 0

GPR00: c00000000085d22c c000000000d0bc80 c000000000d0cc00 8000080080014000

GPR04: 8000080080014000 c00000007ffbf0a0 00010fa060541215 0000000000000000

GPR08: 0000000000000014 0000000000000000 c00000007ffbf000 0000000000000001

GPR12: 0000000024022082 c00000003fff5000 000000007ff5c9b4 000000007faf5248

GPR16: 000000007ff5c9a4 000000000000000a 000000000154931d 0000000001000000

GPR20: 0000000000000001 0000000001000040 0000000000000000 c00000000086df70

GPR24: c000000000d12570 0000000000000200 c000000000a98268 c00000000086b3e0

GPR28: 0000000000000000 00000000000007ff c000000073009000 c000000872fe94c8

NIP ._mpic_map_mmio.isra.12+0x28/0x48

LR ._mpic_map_mmio.isra.12+0x20/0x48

Call Trace:

._mpic_map_mmio.isra.12+0x20/0x48 (unreliable)

.mpic_alloc+0x6bc/0x8bc

.corenet_gen_pic_init+0x4c/0x74

.init_IRQ+0x34/0x4c

.start_kernel+0x304/0x530

start_here_common+0x20/0x5c

Instruction dump:

4c00012c 4e800020 7c0802a6 7c651a14 fbe1fff8 7c9f2378 f8010010 7cc43378

f821ff81 4b7c7d11 60000000 7c690074 7929d182 0b090000 38210080

Kernel panic - not syncing: Attempted to kill th

Thanks & Regards,

Vidya Sagar Pd

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Fri, 02 Jun 2017 11:23:17 GMT

Dear Yiping,

We have 2GB DDR working in the our card.

We observed kernel DMA is consuming all memory log is below:

Zone ranges:
DMA      [mem 0x0000000000000000-0x000000007fffffff]
DMA32    empty
Normal   empty
Movable zone start for each node

In T2080RDB board comes as

Zone ranges:
DMA      [mem 0x0000000000000000-0x000000007fffffff]
DMA32    empty
Normal   [mem 0x0000000080000000-0x00000000ffffffff]
Movable zone start for each node

In our kernel Normal memory allocate as empty.

I am using default SDK2.0 kernel and dts file in present.

Please suggest me how to optimize DMA memory and Normal in the kernel stage.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

yipingwang — Mon, 05 Jun 2017 04:34:31 GMT

Hello Vidya,

Please refer to fixed_sdram in board/freescale/p1010rdb/ddr.c to configure DDR size as 4G, please also configure LAW size as 4G.

Thanks,

Yiping

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Mon, 05 Jun 2017 05:18:21 GMT

Dear Yiping,

u-boot configured for 4G and also in ddr.c.

#define CONFIG_SYS_SDRAM_SIZE 4096u /*2048*/ /* for fixed parameter use */
#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_4G

#define CONFIG_SYS_DDR_CS0_BNDS 0x000000ff

But DDR is getting hanged and allocating only 0 memory of DDR.

Any change is required in tlb.c file, kept default.

Please find ddr.c file in attachment.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Mon, 05 Jun 2017 12:47:09 GMT

Dear Yiping,

We got 4GB DDR memory but kernel gets crash.

MMU: Supported page sizes
         4 KB as direct
      2048 KB as direct & indirect
      4096 KB as direct
     16384 KB as direct
     65536 KB as direct
    262144 KB as direct
   1048576 KB as direct
MMU: Book3E HW tablewalk enabled
bootconsole [udbg0] enabled
CPU maps initialized for 2 threads per core
Starting Linux PPC64 #26 SMP Tue Apr 18 11:45:57 IST 2017
-----------------------------------------------------
ppc64_pft_size    = 0x0
phys_mem_size     = 0x100000000
dcache_line_size = 0x40
icache_line_size = 0x40
cpu_features      = 0x00180480581802c8
possible        = 0x00180480581802c8
always          = 0x00180400581802c0
cpu_user_features = 0xdc008000 0x08000000
mmu_features      = 0x000a0010
firmware_features = 0x0000000000000000
-----------------------------------------------------
<- setup_system()
Linux version 4.1.8-rt8+gbd51baf (imx@imx-laptop) (gcc version 4.9.2 (GCC) ) #26 SMP Tue Apr 18 11:45:57 IST 2017
CoreNet Generic board
Zone ranges:
DMA      [mem 0x0000000000000000-0x000000007fffffff]
DMA32    empty
Normal   [mem 0x0000000080000000-0x00000000ffffffff]
Movable zone start for each node
Early memory node ranges
node   0: [mem 0x0000000000000000-0x00000000ffffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x00000000ffffffff]
MMU: Allocated 2112 bytes of context maps for 255 contexts
PERCPU: Embedded 16 pages/cpu @c0000000ffe00000 s28568 r0 d36968 u131072
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1034240
Kernel command line: root=/dev/mtdblock0 rootfstype=jffs2 rw console=ttyS0,115200 earlyprintk
log_buf_len individual max cpu contribution: 4096 bytes
log_buf_len total cpu_extra contributions: 28672 bytes
log_buf_len min size: 16384 bytes
log_buf_len: 65536 bytes
early log buf free: 12072(73%)
PID hash table entries: 4096 (order: 3, 32768 bytes)
Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
Sorting __ex_table...
Memory: 3964848K/4194304K available (8612K kernel code, 1212K rwdata, 3196K rodata, 360K init, 798K bss, 229456K reserved, 0K cma-reserved)
Hierarchical RCU implementation.
        RCU debugfs-based tracing is enabled.
        CONFIG_RCU_FANOUT set to non-default value of 32
        Additional per-CPU info printed with stalls.
        RCU restricting CPUs from NR_CPUS=24 to nr_cpu_ids=8.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
NR_IRQS:512 nr_irqs:512 16
Unable to handle kernel paging request for data at address 0xc0000008f0fe94c8
Faulting instruction address: 0xc00000000085d234
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=24 CoreNet Generic
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.8-rt8+gbd51baf #26
task: c000000000c33340 ti: c000000000d08000 task.ti: c000000000d08000
NIP: c00000000085d234 LR: c00000000085d22c CTR: 0000000000000000
REGS: c000000000d0ba00 TRAP: 0300   Not tainted (4.1.8-rt8+gbd51baf)
MSR: 0000000080021000 <CE,ME> CR: 84022022 XER: 00000000
DEAR: c0000008f0fe94c8 ESR: 0000000000800000 SOFTE: 0
GPR00: c00000000085d22c c000000000d0bc80 c000000000d0cc00 8000080080012000
GPR04: 8000080080012000 c0000000fffbf090 00010fa060541215 0000000000000000
GPR08: 0000000000000012 0000000000000000 c0000000fffbf000 0000000000000001
GPR12: 0000000024022082 c00000003fff5000 000000007ff5cd24 000000007faf5250
GPR16: 000000007ff5cd14 000000000000000a 00000000e856931d 00000000e8020000
GPR20: 0000000000000001 00000000e8020040 0000000000000000 c00000000086df70
GPR24: c000000000d12570 0000000000000200 c000000000a98268 c00000000086b3e0
GPR28: 0000000000000000 00000000000007ff c0000000f1009000 c0000008f0fe94c8
NIP [c00000000085d234] ._mpic_map_mmio.isra.12+0x28/0x48
LR [c00000000085d22c] ._mpic_map_mmio.isra.12+0x20/0x48
Call Trace:
[c000000000d0bc80] [c00000000085d22c] ._mpic_map_mmio.isra.12+0x20/0x48 (unreliable)
[c000000000d0bd00] [c000000000b9bddc] .mpic_alloc+0x6bc/0x8bc
[c000000000d0be00] [c000000000b9cd44] .corenet_gen_pic_init+0x4c/0x74
[c000000000d0be70] [c000000000b94910] .init_IRQ+0x34/0x4c
[c000000000d0bee0] [c000000000b90a6c] .start_kernel+0x304/0x530
[c000000000d0bf90] [c000000000000544] start_here_common+0x20/0x5c
Instruction dump:
4c00012c 4e800020 7c0802a6 7c651a14 fbe1fff8 7c9f2378 f8010010 7cc43378
f821ff81 4b7c7d11 60000000 7c690074 <f87f0000> 7929d182 0b090000 38210080
---[ end trace dc8fa200cb88537f ]---

Kernel panic - not syncing: Attempted to kill the idle task!
Rebooting in 180 seconds..

Please let me know what i am missing.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

yipingwang — Thu, 15 Jun 2017 07:58:28 GMT

Hello Vidya,

Please configure CMD_MEMTEST, CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END in u-boot and use "mtest" command in u-boot to test DDR memory.

Have a great day,
TIC

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Thu, 15 Jun 2017 08:33:02 GMT

Dear Yiping,

mtest is already implemented in the uboot

#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x00200000
#define CONFIG_SYS_MEMTEST_END 0x00400000

mtest gets pass without any issue.

Please let me know how we can test ECC working status.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

yipingwang — Thu, 15 Jun 2017 08:52:13 GMT

Hello Vidya,

Please boot the system with 32 bit Linux Kernel uImage to check where the Kernel paging error occurs?

In addition, have you used DDRv tool to verify your DDR controller configuration parameters?

Have a great day,
TIC

Re: T2080 discrete DDR3 configuration.

karunakaranradh — Tue, 04 Jul 2017 08:44:12 GMT

Hi Vidya,

Refer: How to Check/Validate DDR3 ECC functionality in T2080 Processor Board? .

U-boot running in single core, your mtest may passed. But you enabled SMPin linux kernel as per your linux log.

Try to boot kernel with single core (NON SMP mode).

Regards,

Karunakaran R

Re: T2080 discrete DDR3 configuration.

yixuanhao — Sun, 05 Nov 2017 13:50:20 GMT

Hi Vidya,

How about your custom T2080 board based on T2080RDB reference design NOW?

Do The DDR3 configturtion with NON-SPD way OK?

I have the SAME QUESTION to U now.

I configed DDR3 refer 1010rdb in uboot source,and read the parameters from cmd "md DDR_REG_CFG_ADDR" at SPD-way u-boot,then,i modified the DDR config.

BUT,still stay at "Waiting for D_INIT timeout. Memory may not work" form serail port show.

I can`t ensure where is wrong for my modified now,and u?

BTW,the code just modified in attachment.

Thanks,

Vidya

Re: T2080 discrete DDR3 configuration.

vidyasagartata — Mon, 06 Nov 2017 12:05:29 GMT

Dear Yixuan,

Yes, our non-spd configuration works fine.

Please verify parameters by using of NXP qcvs tool and validate the DDR3, only test pass then same parameter use in u-boot.

Thanks & Regards, Vidya Sagar

Sent with BlackBerry Work (www.blackberry.com) From: yixuanhao <admin@e3895.dscb.akamaiedge.net>

Sent: 6 Nov 2017 12:39

To: Vidya Sagar <vsprasad@tatapowersed.com>

Subject: Re: - Re: T2080 discrete DDR3 configuration.

yixuan hao replied to the discussion

"Re: T2080 discrete DDR3 configuration."

To view the discussion, visit: https://community.nxp.com/message/958258?commentID=958258&et=watches.email.thread#comment-958258

Re: T2080 discrete DDR3 configuration.

yixuanhao — Mon, 06 Nov 2017 14:25:54 GMT

Dear Vidya Sagar,

Thanks for your help,i verified the parameters form SPD val again,found some differerents and modified,everything is FINE NOW :smileygrin:.

wth my Thanks & Regards,