T-SeriesのトピックRe: T1042 VCORE and VCOREc specs

T1042 VCORE and VCOREc specs

mohsenhaghighat — Tue, 18 Jul 2017 08:44:46 GMT

Hello,

What are the VCORE and VCOREc specs? I want to choose a power supply but i do not know its specs.

I want to design a T1042 custom board and I read the datasheet but i can not find the answre.

thanks.

Re: T1042 VCORE and VCOREc specs

alexander_yakov — Tue, 18 Jul 2017 12:35:04 GMT

Please look T1042 Data Sheet, Table 3 "Recommended operating conditions"

Second column in this table shows all device voltage rails.

As far as I can see, there is no "VCORE" and "VCOREc" voltage rails, the device does not have such rails.

Have a great day,
Alexander
TIC

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Re: T1042 VCORE and VCOREc specs

mohsenhaghighat — Wed, 19 Jul 2017 03:52:28 GMT

Thanks alexander, I means VDD and VDDC, In this table it does not say about the input current or rise time and fall time or slewrate or how much current in 1us it needs? How much noise it can accept?

If I want to use a switching power supply, what does its frequency?

In PCB design how much the distance between 1volt power supply and cpu?

Re: T1042 VCORE and VCOREc specs

alexander_yakov — Wed, 19 Jul 2017 04:09:29 GMT

For VDD and VDDC rails power consumption please look Table 8, note1 below the table.

Re: T1042 VCORE and VCOREc specs

mohsenhaghighat — Wed, 19 Jul 2017 12:31:49 GMT

Thanks Dear Alexander,

We see a t1042 custom board that does not observe power sequencing. This board does not work.

When he changed his board and observe the power sequencing it works.

Is the power sequencing important for T1022 cpu?

If we do not observe power sequencing, the board does not work?

Thanks.

Re: T1042 VCORE and VCOREc specs

alexander_yakov — Wed, 19 Jul 2017 12:37:24 GMT

For power sequencing requirements please look Section 3.2 of device datasheet.

Yes, power sequencing is mandatory.

Re: T1042 VCORE and VCOREc specs

mohsenhaghighat — Wed, 19 Jul 2017 13:10:07 GMT

Thanks Alexander I read this chapter,

I test this sequence, At first 3v3 and 1v8 and 2v5 power on and PORESET is asserted.

Then deassert the PORESET

then vcore power on and then 1v35 power on,

In this sequence the core does not work, But after this when we assert PORESET and deaasert it the cpu works.

where is our problrm?

Re: T1042 VCORE and VCOREc specs

alexander_yakov — Wed, 19 Jul 2017 13:42:52 GMT

Yes.

"1. PORESET_B must be driven asserted before the core and platform power supplies are powered up." - this is said explicitly in note 1 below Table 21.