topic Re: QorIQ T1040 HRESET assertion at PORESET in T-Series

QorIQ T1040 HRESET assertion at PORESET

fdm — Wed, 07 Dec 2016 12:30:14 GMT

Hi,

What conditions should be met in order the T1040 to assert HRESET_B and deassert RESET_REQ_B after assertion of PORESET_B (for example, after RESET_REQ_B assertion during POR sequence)?

I'm observing that both HRESET_B and RESET_REQ_B do not change their states after PORESET_B assertion in my custom board:

Blue - PORESET_B

Magenta - RESET_REQ_B

Green - HRESET_B

BR,

Denis

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Wed, 07 Dec 2016 13:49:16 GMT

Which RCW source is configured?

Does the source provide correct RCW?

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Wed, 07 Dec 2016 14:32:23 GMT

Hi Fedor,

Hard-coded RCW option has been used for the waveform shown.

When using e.g. I2C as RCW source, the HRESET_B is not deasserted in accordance with RM (valid RCW data are not applied yet), but again the RESET_REQ_B is not deasserted after the PORESET_B assertion.

BR,

Denis

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Wed, 07 Dec 2016 14:37:28 GMT

It is required to doublecheck that all notes after the "Table 1. Pinout list by bus" in the "QorIQ T1040, T1020 Data Sheet" are fulfilled, power sequence is correct and all clocks are applied.

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Wed, 07 Dec 2016 15:05:16 GMT

I have only DIFF_SYSCLK ans SD1_REF_CLK1 routed and applied. SYSCLK and DDRCLK are pulled down. Could it be the source of problem?

^{Обновлено}

It seems the RESET_REQ_B is deasserted when HRESET_B is asserted externally (w/o PORESET_B)

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Wed, 07 Dec 2016 15:09:11 GMT

It is required to doublecheck that all notes after the "Table 1. Pinout list by bus" in the "QorIQ T1040, T1020 Data Sheet" are fulfilled.

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Thu, 08 Dec 2016 09:25:23 GMT

I have doublechecked that these requirements are fulfilled and I've also checked that the power sequence is correct.

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Thu, 08 Dec 2016 14:33:19 GMT

> Hard-coded RCW option has been used for the waveform shown.

What are measured voltages of the RCW source signals during POR?

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Thu, 08 Dec 2016 15:47:01 GMT

All of cfg_rcw_src signals are sourced by CPLD during POR. Most of them are not available for measurement.

I've tried to use I2C and SD as the RCW source besides hard-coded (0x9E) option, and at least clock signals have appeared at these interfaces.

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Thu, 08 Dec 2016 16:31:41 GMT

Is TRST_B asserted during POR?

Also please check IFC_WE0_B behaviour during POR.

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Fri, 09 Dec 2016 07:42:34 GMT

Yes, TRST_B is tied to PORESET_B now.

IFC_WE0_B is at low level well before PORESET_B negation (~800us) and at least 100ns (10 x Tsysclk) after.

Stable DIFF_SYSCLK is applied at least 700us before PORESET_B negation.

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Fri, 09 Dec 2016 07:47:19 GMT

Please create Technical Case and provide the processor connection schematics for inspection as searchable PDF.

https://community.freescale.com/thread/381898

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Sat, 10 Dec 2016 12:45:34 GMT

Finally I have solved this puzzle!

Unlike other POR config inputs (cfg_rcw_src[0:8]), the cfg_eng_use[0:2] inputs must be in a valid state not only at the moment of POR deassertion, but all the time during the PORESET_B assertion.

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Sat, 10 Dec 2016 16:53:30 GMT

It is always reasonable to refer to the processor's Data Sheet:

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Sat, 10 Dec 2016 17:59:11 GMT

These setup and hold times are relative to negation of PORESET_B, that is to the moment of PORESET_B deassertion!

There's nothing about POR config inputs, and particularly about cfg_eng_use[0:2], during PORESET_B assertion, besides the last 4T (=40ns @ Fsysclk=100MHz), isn't it?

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Sun, 11 Dec 2016 03:42:47 GMT

> isn't it?

No - refer to the Design Checklist.

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Sun, 11 Dec 2016 20:45:00 GMT

Are you trying to convince me that the documentation is clear enough?

"Some signals must be driven high or low during the reset period. For details about all the signals that require external pull-up resistors, see the data sheet document." - are you saying about this?

Well, let's see:

Which of these notes are definitely saying about the need to drive the signals during all time while the PORESET_B is active?

On the other hand, the Design Checklist says that:

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Mon, 12 Dec 2016 02:32:03 GMT

> need to drive the signals during all time while the PORESET_B is active

The "all time" definitely is not required.

Re: QorIQ T1040 HRESET assertion at PORESET

fdm — Mon, 12 Dec 2016 12:46:25 GMT

Well, what time is required?

Re: QorIQ T1040 HRESET assertion at PORESET

ufedor — Mon, 12 Dec 2016 13:24:52 GMT

As specified in the T1040 Data Sheet, Table 21.