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    <title>topic Re: DDR3 Power Connection on T1024RDB  in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/DDR3-Power-Connection-on-T1024RDB/m-p/653239#M1871</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/17137i1FA7986E540EEE2F/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;This figure is from T1040QDS schematics where they explains that connection. For the T1024RDB schematics it should sounds like “Decoupling between 1V35_SLP and 1V35 power split located under DIMM. Place these caps around DDR Power Pin areas to stitch return current flow for Address and command signals.”&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 07 Dec 2016 13:08:37 GMT</pubDate>
    <dc:creator>r8070z</dc:creator>
    <dc:date>2016-12-07T13:08:37Z</dc:date>
    <item>
      <title>DDR3 Power Connection on T1024RDB</title>
      <link>https://community.nxp.com/t5/T-Series/DDR3-Power-Connection-on-T1024RDB/m-p/653238#M1870</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Below is the power connection of the DDR3 that is presented on the T1024RDB schematic. I couldn't understand why such a connection (highlighted portion)&amp;nbsp;is made.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="ddr3.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/15523i352C77DE7A1F2B44/image-size/large?v=v2&amp;amp;px=999" role="button" title="ddr3.PNG" alt="ddr3.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Dec 2016 05:55:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/DDR3-Power-Connection-on-T1024RDB/m-p/653238#M1870</guid>
      <dc:creator>bltuna</dc:creator>
      <dc:date>2016-12-07T05:55:35Z</dc:date>
    </item>
    <item>
      <title>Re: DDR3 Power Connection on T1024RDB</title>
      <link>https://community.nxp.com/t5/T-Series/DDR3-Power-Connection-on-T1024RDB/m-p/653239#M1871</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/17137i1FA7986E540EEE2F/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;This figure is from T1040QDS schematics where they explains that connection. For the T1024RDB schematics it should sounds like “Decoupling between 1V35_SLP and 1V35 power split located under DIMM. Place these caps around DDR Power Pin areas to stitch return current flow for Address and command signals.”&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Dec 2016 13:08:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/DDR3-Power-Connection-on-T1024RDB/m-p/653239#M1871</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2016-12-07T13:08:37Z</dc:date>
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