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    <title>topic Re: T1042 DDR Validation in T-Series</title>
    <link>https://community.nxp.com/t5/T-Series/T1042-DDR-Validation/m-p/632285#M1720</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Starting from a configuration that passes Operational DDR tests, try to run Centering the clock. Note that only Operational DDR tests doesn't change the configuration. The other tests will change the configuration.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Adrian&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Apr 2017 06:04:51 GMT</pubDate>
    <dc:creator>addiyi</dc:creator>
    <dc:date>2017-04-26T06:04:51Z</dc:date>
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      <title>T1042 DDR Validation</title>
      <link>https://community.nxp.com/t5/T-Series/T1042-DDR-Validation/m-p/632284#M1719</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using the T1042 processor with DDR4 RAM in my design. The configuration is x32 plus x8 mode with each DDR having x16 width. While using the DDR validation tool I am able to get 100 percent pass for the following tests:&lt;/P&gt;&lt;P&gt;Read ODT and Driver&lt;/P&gt;&lt;P&gt;Write ODT and driver&lt;/P&gt;&lt;P&gt;Operational DDR tests.&lt;/P&gt;&lt;P&gt;But while doing the Centering the Clock it is failing for the clock adjust value and WRLVL margin per byte lane. The error that comes is configuration error.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Following are the snapshots&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/11128iDBDBFF60C9AED062/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.jpg" alt="pastedImage_1.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/11286iD9156E84F7886490/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.jpg" alt="pastedImage_2.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/11290iBDDA01F7F5E18A68/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.jpg" alt="pastedImage_3.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_4.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/11266i138C8960E1A7C426/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_4.jpg" alt="pastedImage_4.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anyone help me out with this. I would like to know how to fix this issue and also what are the usual reasons for this issue. I would also like to know what this configuration error is.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&amp;nbsp;&lt;/P&gt;&lt;P&gt;Gokul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Apr 2017 11:12:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1042-DDR-Validation/m-p/632284#M1719</guid>
      <dc:creator>gokulkrishnan</dc:creator>
      <dc:date>2017-04-21T11:12:45Z</dc:date>
    </item>
    <item>
      <title>Re: T1042 DDR Validation</title>
      <link>https://community.nxp.com/t5/T-Series/T1042-DDR-Validation/m-p/632285#M1720</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Starting from a configuration that passes Operational DDR tests, try to run Centering the clock. Note that only Operational DDR tests doesn't change the configuration. The other tests will change the configuration.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Adrian&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Apr 2017 06:04:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T1042-DDR-Validation/m-p/632285#M1720</guid>
      <dc:creator>addiyi</dc:creator>
      <dc:date>2017-04-26T06:04:51Z</dc:date>
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