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    <title>T-SeriesのトピックCLK for DDR4</title>
    <link>https://community.nxp.com/t5/T-Series/CLK-for-DDR4/m-p/625511#M1665</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using a x8 configuration for DDR4, ie 8 chips for data and one for ECC. Now each chip requires clock. The processor I'm using is T1042. t has two clock outputs ( CLK 0 and 1). So how should I connect them ??&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you let me know about the CKE as well.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&amp;nbsp;&lt;/P&gt;&lt;P&gt;Gokul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 25 Nov 2016 13:27:11 GMT</pubDate>
    <dc:creator>gokulkrishnan</dc:creator>
    <dc:date>2016-11-25T13:27:11Z</dc:date>
    <item>
      <title>CLK for DDR4</title>
      <link>https://community.nxp.com/t5/T-Series/CLK-for-DDR4/m-p/625511#M1665</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am using a x8 configuration for DDR4, ie 8 chips for data and one for ECC. Now each chip requires clock. The processor I'm using is T1042. t has two clock outputs ( CLK 0 and 1). So how should I connect them ??&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you let me know about the CKE as well.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&amp;nbsp;&lt;/P&gt;&lt;P&gt;Gokul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 25 Nov 2016 13:27:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/CLK-for-DDR4/m-p/625511#M1665</guid>
      <dc:creator>gokulkrishnan</dc:creator>
      <dc:date>2016-11-25T13:27:11Z</dc:date>
    </item>
    <item>
      <title>Re: CLK for DDR4</title>
      <link>https://community.nxp.com/t5/T-Series/CLK-for-DDR4/m-p/625512#M1666</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Have a great day,&lt;/P&gt;&lt;P&gt;The T1042 supports 32-bit and 64-bit DDR data bus width. I suppose that you are going implement the 64-bit data bus so all 8 chips will be connected to the same chip select MSC0 ( or MCS1). In this case they all ought be connected to the same clock enable CKE0 if MCS0 (or CKE1 if MCS1) is used. The fly-by routing is recommended for address, command, control, and clock signal bus. You may use single differential clock pair for all 8 chips in fly-by mode. Any of the MCKE0/MCKE0 or MCKE1/MCKE1 can be used.&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Nov 2016 09:00:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/CLK-for-DDR4/m-p/625512#M1666</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2016-11-28T09:00:09Z</dc:date>
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