L2 cache coherence issue on e6500 Rev-2.0

yintai_shao — Tue, 01 Nov 2016 07:30:32 GMT

There is an e6500 L2 cache issue perplexed me.

Target board: T4240QDS and T2080QDS

Core version: e6500 REV-2.0

OS: WindRiver's VxWorks SMP system

Boot loader: u-boot

Phenomenon description:

In my test case, one of the T4240 (or T2080) core continues to write an increased value to a specified memory address (this space is pointed by pMemAddr). The address is could be accessed for other cores. The operation just likes,

*(volatile UINT32 *)(pMemAddr) = 0;

while (testRun)

{

(*(volatile unsigned int *)(pMemAddr))++;

}

This core, I name it as writer in here.

Another core continues to check whether the context in the memory address is changed or not. I named this core as reader. The reader just could find the context in the memory (pointed by pMemAddr) is changed from the initialized value (deadbeef) to 0 and kept, no more changed again.

If the write instruction in the loop is followed by a memory barrier instruction, then the reader could find the memory context is changed in real time, the coherence issue will be no more.

*(volatile UINT32 *)(pMemAddr) = 0;

while (testRun)

{

(*(volatile unsigned int *)(pMemAddr))++;

__asm volatile(" sync ");

}

This issue is occurred only on CPU with e6500 REV-2.0 core, such as T4240 REV-2.0 and T2080 REV-1.0, but not on T4240 REV-1.0 (e6500 REV-1.0), e5500 core types (T1040E) and e500mc types (P4080E).

Why this issue occurred?

What is difference between e6500 REV-1.0 and REV-2.0?

Whether is the memory barrier instruction is needed on this condition the in normal?

Thanks

Yintai Shao

topic L2 cache coherence issue on e6500 Rev-2.0 in T-Series

L2 cache coherence issue on e6500 Rev-2.0