T-Series中的主题 Re: T1040 Clock Query

T1040 Clock Query

gokulkrishnan — Fri, 28 Oct 2016 07:48:40 GMT

Hi,

I am using a T1040 processor. The clock signals to the chip, DIFF_SYS_CLK p and n can be supplied with a 3.3V input oscillator or do we need to give 1.8V itself. Do these pins have internal pull ups?

Could you help me with the voltage levels of the other clocks as well namely.

1. DDR Clock

2. System Clock

3. USB clock

Regards

Gokul

Re: T1040 Clock Query

ufedor — Fri, 28 Oct 2016 08:14:12 GMT

All mentioned clock signals belong to the OVDD(OVDD1) domain - refer to the QorIQ T2080 Data Sheet, Table 1. Pinout list by bus.

OVDD(OVDD1) could be only 1.8V – refer to the QorIQ T2080 Data Sheet, Table 3. Recommended operating conditions.

So SYSCLK, DDRCLK and USBCLK have to have 1.8V amplitude.

> DIFF_SYS_CLK p and n can be supplied with a 3.3V input oscillator?

No.

Refer to the QorIQ T2080 Data Sheet, 3.6.6.1 Differential System clock DC timing specifications.

Re: T1040 Clock Query

gokulkrishnan — Fri, 28 Oct 2016 10:20:36 GMT

Hi,

Do these clocks have internal pull ups so that we can use an ac caps to adjust the dc level !

Re: T1040 Clock Query

ufedor — Fri, 28 Oct 2016 16:45:57 GMT

There are no internal pull-ups.

Re: T1040 Clock Query

gokulkrishnan — Mon, 31 Oct 2016 10:53:30 GMT

Hi,

Could you suggest apart number for the Differential system clock 100 MHz. I am unable to find one that suffice the requirements given in table 14 of the datasheet. The swing shwn is 1.08V to 1.8v right ?

Regards

Gokul

Re: T1040 Clock Query

ufedor — Mon, 31 Oct 2016 15:13:31 GMT

IDT9FGV0641

Refer to the T1040RDB design files:

http://cache.nxp.com/files/32bit/hardware_tools/schematics/T1040RDB_DESIGNFILES.zip

Re: T1040 Clock Query

gokulkrishnan — Tue, 01 Nov 2016 13:33:34 GMT

Hi,

For the DDR clock of the chip, I am unable to find a part. te reference schematic sgiven do not have a part specified either. Do you have any recommendations for the same that falls within the specified swing of 1.08 to 1.8v.

Re: T1040 Clock Query

ufedor — Tue, 01 Nov 2016 13:49:39 GMT

Please see attached.

Re: T1040 Clock Query

fdm — Thu, 03 Nov 2016 08:20:36 GMT

Hi Fedor,

Would you confirm the necessity of an external biasing at the DIFF_SYSCLK input in case of AC-coupling?

This seems contradicting with datasheet and also with this response given on my similar question (see also this topic).

BR,

Denis

Re: T1040 Clock Query

gokulkrishnan — Mon, 05 Dec 2016 08:16:52 GMT

Hi,

For this device do we need to add any termination. the datasheet does not have any specifications.

Regards

Gokul

Re: T1040 Clock Query

ufedor — Mon, 05 Dec 2016 08:18:45 GMT

Which termination is in question?

Re: T1040 Clock Query

gokulkrishnan — Mon, 05 Dec 2016 09:39:31 GMT

Hi,

The termination for the clock source you had the mentioned. SMB-066660-7BY0T0.

Regards

Gokul

Re: T1040 Clock Query

ufedor — Mon, 05 Dec 2016 11:47:27 GMT

On the T1040D4RDB 33Ohm serial resistor is inserted.

It is recommend to perform a simulation to check whether such termination is suitable for a custom board.