topic Re: How to reset DDR controller in T1024? in T-Series

How to reset DDR controller in T1024?

veerendranathj — Mon, 09 Jan 2017 10:49:44 GMT

Hi ,

I am transferring control from u-boot to my bare board binary(which will execute from NOR flash). Now I want reset the DDR controller and re-initialize. I tried to reset using "DDR_DDR_SDRAM_CFG_3" reset but after i could not inialize RAM memory... Please refer below for my code... Pleas let me know if am doing anything wrong...

asm ("ddr_cntrl_reset:");
SET_GROUP_BASE(CCSRBAR + DDRC_GROUP_OFFSET);
//# DDR_SDRAM_CFG
CCSR_SET_W(0x110, 0x0); // Disabling DDR controller
//# DDR_SDRAM_CFG_3
CCSR_SET_W(0x260, 0x80000000); // Reset ddr controller.
//# wait for DDRC_RST bits to clear
asm ("xor 6, 6, 6");
asm ("oris 6, 6, 0x80000000@h");
asm ("ori 6, 6, 0x80000000@l");
asm ("ddr_reset_loop:");
CCSR_GET_W(0x260); // Will fetch the value to register 19
asm ("andis. 19, 19, 0x8000");
asm ("cmpw 19, 6");
asm ("bt eq, ddr_reset_loop");

asm ("ddr_cntrl_reset_end:");

// Re-initializing DDR
//# DDR_SDRAM_CFG
CCSR_SET_W(0x110, 0x67044000);
//# DDR_CS0_BNDS
CCSR_SET_W(0x000, 0x0000007F);
//# DDR_CS1_BNDS
CCSR_SET_W(0x008, 0x0000007F);
//# DDR_CS0_CONFIG
CCSR_SET_W(0x080, 0x80044302);
//# DDR_CS1_CONFIG
CCSR_SET_W(0x084, 0x80004302);
//# DDR_CS0_CONFIG_2
CCSR_SET_W(0x0c0, 0x00000000);
//# DDR_CS1_CONFIG_2
CCSR_SET_W(0x0c4, 0x00000000);
//# DDR_TIMING_CFG_3
CCSR_SET_W(0x100, 0x01071000);
//# DDR_TIMING_CFG_0
CCSR_SET_W(0x104, 0x50110004);
//# DDR_TIMING_CFG_1
CCSR_SET_W(0x108, 0xBCB48C56);
//# DDR_TIMING_CFG_2
CCSR_SET_W(0x10c, 0x0040C0D8);
//# DDR_SDRAM_CFG_2
CCSR_SET_W(0x114, 0x00401111);
//# DDR_SDRAM_MODE
CCSR_SET_W(0x118, 0x00441C70);
//# DDR_SDRAM_MODE_2
CCSR_SET_W(0x11c, 0x00980000);
//# DDR_SDRAM_MODE_4
CCSR_SET_DUP_W(0x204);
//# DDR_SDRAM_MODE_6
CCSR_SET_DUP_W(0x20C);
//# DDR_SDRAM_MODE_8
CCSR_SET_DUP_W(0x214);
//# DDR_SDRAM_MODE_3
CCSR_SET_W(0x200, 0x00001C70);
//# DDR_SDRAM_MODE_5
CCSR_SET_DUP_W(0x208);
//# DDR_SDRAM_MODE_7
CCSR_SET_DUP_W(0x210);
//# DDR_SDRAM_MD_CNTL
CCSR_SET_W(0x120, 0x00000000);
//# DDR_SDRAM_INTERVAL
CCSR_SET_W(0x124, 0x0C300100);
//# DDR_DATA_INIT
CCSR_SET_W(0x128, 0xDEADBEEF);
//# DDR_SDRAM_CLK_CNTL
CCSR_SET_W(0x130, 0x02000000);
//# DDR_INIT_ADDR
CCSR_SET_W(0x148, 0x00000000);
//# DDR_INIT_EXT_ADDR
CCSR_SET_DUP_W(0x14c);
//# TIMING_CFG_4
CCSR_SET_W(0x160, 0x00000001);
//# TIMING_CFG_5
CCSR_SET_W(0x164, 0x04401400);
//# DDR_ZQ_CNTL
CCSR_SET_W(0x170, 0x89080600);
//# DDR_WRLVL_CNTL
CCSR_SET_W(0x174, 0xC675F607);
//# DDR_SR_CNTR
CCSR_SET_W(0x17c, 0x00000000);
//# DDR_WRLVL_CNTL_2
CCSR_SET_W(0x190, 0x0808090B);
//# DDR_WRLVL_CNTL_3
CCSR_SET_W(0x194, 0x0C0D0E0A);
//# DDR_DDRCDR_1
CCSR_SET_W(0xb28, 0x80000000);
//# DDRCDR_2
CCSR_SET_W(0xb2c, 0x00000000);
//# DDR_ERR_DISABLE - DISABLE
CCSR_SET_W(0xe44, 0x00000000);
//# ERR_SBE
CCSR_SET_W(0xe58, 0x00000000);

//# delay before enable
asm ("lis 5, 0x0000");
asm ("ori 5, 5, 0x0fff");
asm ("mtspr 9 ,5");
asm ("wait_loop1:");
asm ("bc 16, 0, wait_loop1 ");

//# DDR_SDRAM_CFG
CCSR_SET_W(0x110, 0xE7044000);

//# wait for DRAM data initialization
asm ("lis 5, 0x0000");
asm ("ori 5, 5, 0x2ffd");
asm ("mtspr 9 ,5");
asm ("wait_loop2:");
asm ("bc 16,0,wait_loop2 ");

//# wait for D_INIT bits to clear
asm ("xor 5, 5, 5");
asm ("wait_loop3:");
CCSR_GET_W(0x114);
asm ("mr 5, 19");
asm ("rlwinm 5, 5, 0, 27, 27");
asm ("cmpwi 5, 0x0010");
asm ("bt eq, wait_loop3");

Regards,

Veerendranath

Re: How to reset DDR controller in T1024?

alexander_yakov — Mon, 09 Jan 2017 12:59:32 GMT

Sorry, it is not clear what is the reason why you want to re-initialize DDR in u-boot, this is done already in u-boot and no more re-initializations necessary.

Have a great day,
Alexander

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Re: How to reset DDR controller in T1024?

veerendranathj — Mon, 09 Jan 2017 13:24:42 GMT

I am writing bare board application(Hardware testing software) which will test peripherals and interfaces of our product which is based on T1024 processor. I am prototyping the test application on T1024RDB. We are using u-boot as bootloader for actual product software and test software(which I am working). As part some requirement I need to reinitialize the DDR controller in test software.

Regards,

Veerendranath

Re: How to reset DDR controller in T1024?

alexander_yakov — Mon, 09 Jan 2017 13:40:51 GMT

I do not think it is possible to re-initialize DDR controller from user software running from u-boot shell, because u-boot itself uses DDR memory for its operation.

Re: How to reset DDR controller in T1024?

veerendranathj — Mon, 09 Jan 2017 14:49:51 GMT

My test application is bare board binary which will be executed in Hypervisor mode. Once control transfers to my application by u-boot(using "go" command). u-boot won't have any control as the test application will be running in Hyper-visor mode(which is highest privilege mode). As the test application executing from NOR flash there should be no issue in re-initializing the DDR controller.

But here my concern is why reset functionality(using DDR_SDRAM_CFG_3) is not working as expected.

Even if I don't use u-boot(I booting the board using my test application it self) DDR controller reset functionality is not working as expected. (as per some test requirements my test application needs to reset the DDR controller).

After setting the reset bit in DDR_SDRAM_CFG_3... it's getting auto clear as per T1024 reference manual... but data initialization is not completing... it's keep on waiting for DATA_INIT bit to clear...

Re: How to reset DDR controller in T1024?

alexander_yakov — Thu, 12 Jan 2017 04:21:36 GMT

So, if my understanding is correct, you have working hardware, I mean your memory works properly under u-boot with settings, used by uboot. After you transfer control to your software, you can reset DDR controller (you can see DDRC_RST bit is successfuly self-cleared), but after reset, when you place your own settings to DDR controller, it can not successfuly finish initialization. In this case recommend referring your u-boot code for proper DDR settings and proper DDR initialization sequence used by u-boot and already verified as working properly.

Re: How to reset DDR controller in T1024?

veerendranathj — Thu, 12 Jan 2017 04:39:47 GMT

I have tested my DDR configuration code without u-boot by booting board with my application... it is absolutely working fine... But I am facing the problem when I reset and initialize the DDR controller...

Re: How to reset DDR controller in T1024?

alexander_yakov — Thu, 12 Jan 2017 07:03:59 GMT

When DDR controller is disabled by MEM_EN, the DDR memory itself must be also reset.

The following is said in Section 14.5.3 of T1024 Reference Manual:

Application system board must assert the reset signal on DDR
memory devices until software is able to program the DDR
memory controller configuration registers, and must deassert
the reset signal on DDR memory devices before
DDR_SDRAM_CFG[MEM_EN] is set. This ensures that the
DDR memory devices are held in reset until a stable clock is
provided and, further, that a stable clock is provided before
memory devices are released from reset.