topic How to disable cache coherence on e6500? in T-Series

How to disable cache coherence on e6500?

janewhitman — Mon, 05 Sep 2016 11:45:54 GMT

Hello,

I was wondering whether there is a way to disable cache coherence on e6500. I wouldn't like to turn off the caches completely. Any suggestions on this?

Thanks!

Re: How to disable cache coherence on e6500?

alexander_yakov — Tue, 06 Sep 2016 11:55:31 GMT

Please look e6500 core Reference Manual, Section 5.6.2 "Enabling and disabling the L1 caches".

Hope this what you asking for.

Have a great day,
Alexander

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Re: How to disable cache coherence on e6500?

janewhitman — Tue, 06 Sep 2016 12:07:35 GMT

Hi Alexander,
unfortunately, I cannot find anything related to coherence in that section.

However, I discovered TLB entry fields today, so I hope it's the right direction.

Thank you,

Re: How to disable cache coherence on e6500?

michelle — Tue, 06 Sep 2016 21:04:03 GMT

Coherence is a TLB bit (the M bit) which tells corenet to snoop caches and changes core behavior towards that region of memory to coherent (it impacts many instructions' behavior). The caches themselves are a separate issue. What are you trying to do? Run with caches off? Don't Performance would be awful. Run without a cohrenence domain for a memory region? That might make more sense but goes quite off the reservation for the standard supplied SDK and other NXP reference software...