<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>T-SeriesのトピックQorIQ T1040 DIFF_SYSCLK input specifications</title>
    <link>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400665#M124</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to T1040 Family Design Checklist, DIFF_SYSCLK input is &lt;EM&gt;"LVDS type clock buffer with AC/DC characteristics identical to the SerDes reference clock inputs which are HCSL-compatible"&lt;/EM&gt;.&lt;/P&gt;&lt;P&gt;Section 3.6.6.1 of T1040 DS "Differential System clock DC timing specifications" says &lt;EM&gt;"For DC timing specification, see (3.22.2.3) &lt;SPAN style="text-decoration: underline;"&gt;DC-level requirement for SerDes reference clocks&lt;/SPAN&gt;"&lt;/EM&gt;.&lt;/P&gt;&lt;P&gt;Section 3.22.2.3 constrains input CM voltage between 100 mV and 400 mV for an external DC-coupled connection based on the assumption of maximum average current allowed for each input pin (8 mA).&lt;/P&gt;&lt;P&gt;Is this constraint applicable to the DIFF_SYSCLK input (it seems very doubtful)?&lt;/P&gt;&lt;P&gt;Is there an internal biasing circuit at the DIFF_SYSCLK input or it should be added externally in the case of AC coupling?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;BR,&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&amp;nbsp;&amp;nbsp; Denis&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 22 Sep 2015 15:10:17 GMT</pubDate>
    <dc:creator>fdm</dc:creator>
    <dc:date>2015-09-22T15:10:17Z</dc:date>
    <item>
      <title>QorIQ T1040 DIFF_SYSCLK input specifications</title>
      <link>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400665#M124</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to T1040 Family Design Checklist, DIFF_SYSCLK input is &lt;EM&gt;"LVDS type clock buffer with AC/DC characteristics identical to the SerDes reference clock inputs which are HCSL-compatible"&lt;/EM&gt;.&lt;/P&gt;&lt;P&gt;Section 3.6.6.1 of T1040 DS "Differential System clock DC timing specifications" says &lt;EM&gt;"For DC timing specification, see (3.22.2.3) &lt;SPAN style="text-decoration: underline;"&gt;DC-level requirement for SerDes reference clocks&lt;/SPAN&gt;"&lt;/EM&gt;.&lt;/P&gt;&lt;P&gt;Section 3.22.2.3 constrains input CM voltage between 100 mV and 400 mV for an external DC-coupled connection based on the assumption of maximum average current allowed for each input pin (8 mA).&lt;/P&gt;&lt;P&gt;Is this constraint applicable to the DIFF_SYSCLK input (it seems very doubtful)?&lt;/P&gt;&lt;P&gt;Is there an internal biasing circuit at the DIFF_SYSCLK input or it should be added externally in the case of AC coupling?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;BR,&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&amp;nbsp;&amp;nbsp; Denis&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 22 Sep 2015 15:10:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400665#M124</guid>
      <dc:creator>fdm</dc:creator>
      <dc:date>2015-09-22T15:10:17Z</dc:date>
    </item>
    <item>
      <title>Re: QorIQ T1040 DIFF_SYSCLK input specifications</title>
      <link>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400666#M125</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt; &lt;/P&gt;&lt;P&gt; Yes the section 3.22.2.3 constrains applicable to the DIFF_SYSCLK input for an external DC-coupled connection. Table 34 of the design checklist shows recommended external DC-coupled connections to different clock source types.&lt;/P&gt;&lt;P&gt;In case of AC coupling input external biasing circuit is not required at the DIFF_SYSCLK input. Recommended&amp;nbsp; AC-coupled connections you can find in Freescale application note AN3411 “SerDes Reference Clock Interfacing and HSSI Measurements Recommendations”&lt;/P&gt;&lt;P&gt; &lt;SPAN lang="EN-US" style="font-size: 12.0pt; font-family: 'Times New Roman';"&gt;&lt;A class="jive-link-external-small" data-content-finding="Community" href="https://www.freescale.com/webapp/Download?colCode=AN4311" rel="nofollow"&gt;https://www.freescale.com/webapp/Download?colCode=AN4311&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Sep 2015 07:20:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400666#M125</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2015-09-23T07:20:49Z</dc:date>
    </item>
    <item>
      <title>Re: QorIQ T1040 DIFF_SYSCLK input specifications</title>
      <link>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400667#M126</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Serguei,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What range of the CM voltage is allowed at the DIFF_SYSCLK input?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;BR,&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&amp;nbsp;&amp;nbsp; Denis&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 23 Sep 2015 09:30:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400667#M126</guid>
      <dc:creator>fdm</dc:creator>
      <dc:date>2015-09-23T09:30:42Z</dc:date>
    </item>
    <item>
      <title>Re: QorIQ T1040 DIFF_SYSCLK input specifications</title>
      <link>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400668#M127</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;I was informed from SOC design that there is no internal AC coupling in the&amp;nbsp;DIFF_SYSCLK clock receiver. So&amp;nbsp;AN3411&amp;nbsp; cannot be directly applied to this inputs.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;The data sheet specifies the input common mode voltage range as 50mv - 1570 mV.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Nov 2016 14:34:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/QorIQ-T1040-DIFF-SYSCLK-input-specifications/m-p/400668#M127</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2016-11-03T14:34:46Z</dc:date>
    </item>
  </channel>
</rss>

