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    <title>T-SeriesのトピックRe: T2081 DDR3L on-board initialisation</title>
    <link>https://community.nxp.com/t5/T-Series/T2081-DDR3L-on-board-initialisation/m-p/553633#M1144</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;NXP SDK supports the T208xQDS and T208sRDB boards. U-boot for these boards uses SPD for DDR configuring. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;See the t208xrdb.zip file in the attachment.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;Find the following line in the ddr.h file:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;static const struct board_specific_parameters udimm0[] = { &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;This structure contains the following parameters:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;n_ranks, datarate_mhz_high, rank_gb, clk_adjust, wrlvl_start, wrlvl_ctl_2, wrlvl_ctl_3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;Look at the T1023RDB setting in the t102xrdb.h file. Find the CONFIG_SYS_DDR_RAW_TIMING in this file. This setting provides do not use SPD for DDR configuring. See the&amp;nbsp; t102xrdb.h and ddr_t102xrdb.c files for the T102sRDB board from u-boot. See the ddr_raw_timing procedure in the ddr_t102xrdb.c file.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;Use similar method for your T2081 board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Pavel Chubakov&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 Jul 2016 07:29:10 GMT</pubDate>
    <dc:creator>Pavel</dc:creator>
    <dc:date>2016-07-11T07:29:10Z</dc:date>
    <item>
      <title>T2081 DDR3L on-board initialisation</title>
      <link>https://community.nxp.com/t5/T-Series/T2081-DDR3L-on-board-initialisation/m-p/553632#M1143</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;WE are using a T2081 with on-board 4x DDR3L 4Gb&amp;nbsp; 256Mx16/ MT41K256M16-1600 , so we do not have on-board&amp;nbsp; SPD. Can you supply us&amp;nbsp; data to fill the dimm_param_s data structure used by UBOOT ?&lt;/P&gt;&lt;P&gt;Best rgards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 08 Jul 2016 14:27:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2081-DDR3L-on-board-initialisation/m-p/553632#M1143</guid>
      <dc:creator>ioxos</dc:creator>
      <dc:date>2016-07-08T14:27:12Z</dc:date>
    </item>
    <item>
      <title>Re: T2081 DDR3L on-board initialisation</title>
      <link>https://community.nxp.com/t5/T-Series/T2081-DDR3L-on-board-initialisation/m-p/553633#M1144</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;NXP SDK supports the T208xQDS and T208sRDB boards. U-boot for these boards uses SPD for DDR configuring. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;See the t208xrdb.zip file in the attachment.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;Find the following line in the ddr.h file:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;static const struct board_specific_parameters udimm0[] = { &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;This structure contains the following parameters:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;n_ranks, datarate_mhz_high, rank_gb, clk_adjust, wrlvl_start, wrlvl_ctl_2, wrlvl_ctl_3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;Look at the T1023RDB setting in the t102xrdb.h file. Find the CONFIG_SYS_DDR_RAW_TIMING in this file. This setting provides do not use SPD for DDR configuring. See the&amp;nbsp; t102xrdb.h and ddr_t102xrdb.c files for the T102sRDB board from u-boot. See the ddr_raw_timing procedure in the ddr_t102xrdb.c file.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="xmsonormal" style="margin-bottom: .0001pt; background: white;"&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt;"&gt;Use similar method for your T2081 board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Pavel Chubakov&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Jul 2016 07:29:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/T-Series/T2081-DDR3L-on-board-initialisation/m-p/553633#M1144</guid>
      <dc:creator>Pavel</dc:creator>
      <dc:date>2016-07-11T07:29:10Z</dc:date>
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