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    <title>topic S32V: SRC_GPR Registers: Write failures? in S32V</title>
    <link>https://community.nxp.com/t5/S32V/S32V-SRC-GPR-Registers-Write-failures/m-p/734680#M93</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm trying to configure the PCIE related registers on the S32v EVB board and I keep encountering strange behaviour.&lt;/P&gt;&lt;P&gt;For example, once QNX is up and running on the S32V EVB board, I tried reading the SRC_GPR5 register (address: 0x4007C110). The read succeeded and I got the following value -- 0x12500208 .&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However, if I try to write to this register after the OS has booted, I get a bus error.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I can easily configure this registers in IPL and u-boot. I can't seem to do it after QNX is up and running. I've checked that the register itself is R/W and is a non-secure register (based on the TRM).&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can someone let me know if the TRM was updated or there is anything special I need to do to write to these registers once the OS is up and running?&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ekta&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 09 Feb 2018 18:03:48 GMT</pubDate>
    <dc:creator>ektasachdev</dc:creator>
    <dc:date>2018-02-09T18:03:48Z</dc:date>
    <item>
      <title>S32V: SRC_GPR Registers: Write failures?</title>
      <link>https://community.nxp.com/t5/S32V/S32V-SRC-GPR-Registers-Write-failures/m-p/734680#M93</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm trying to configure the PCIE related registers on the S32v EVB board and I keep encountering strange behaviour.&lt;/P&gt;&lt;P&gt;For example, once QNX is up and running on the S32V EVB board, I tried reading the SRC_GPR5 register (address: 0x4007C110). The read succeeded and I got the following value -- 0x12500208 .&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;However, if I try to write to this register after the OS has booted, I get a bus error.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I can easily configure this registers in IPL and u-boot. I can't seem to do it after QNX is up and running. I've checked that the register itself is R/W and is a non-secure register (based on the TRM).&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can someone let me know if the TRM was updated or there is anything special I need to do to write to these registers once the OS is up and running?&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Thanks,&lt;/P&gt;&lt;P&gt;Ekta&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Feb 2018 18:03:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32V/S32V-SRC-GPR-Registers-Write-failures/m-p/734680#M93</guid>
      <dc:creator>ektasachdev</dc:creator>
      <dc:date>2018-02-09T18:03:48Z</dc:date>
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