topic I2S data transfer via DMA in S32 SDK

I2S data transfer via DMA

Mohit_Manvar — Tue, 06 Feb 2024 13:57:22 GMT

HW: S32K144 eval board

Hi experts,

I am using S32K144 with S32 design studio IDE. I want to transfer I2S(FlexIO) data with the help of DMA but don't know How can I configure. mainly I want to send continuous data on I2S.
I need help to implement logic for same. I go through example project of DMA but in that only transferring virtual to one buffer to another.

Please arrange a call so I can discuss for implementation help or share sample code which can transfer data via DMA over I2S.

Regards,

Mohit

Re: I2S data transfer via DMA

Julián_AragónM — Tue, 06 Feb 2024 17:16:28 GMT

Hi @Mohit_Manvar,

Hope you are doing well! Please help me with more details about your desired implementation. I see that you added S32 SDK as a label, are you using SDK or RTD for drivers? Please specify the version as well.

If you are using RTD, there is a chapter on RTD_I2S_UM named 3.6.3 I2s over SAI DMA transfer which include some driver usage and configuration tips for I2S.

As for the call, I apologize for any inconveniences this may cause, but this open forum is only for messages/posts.

Best regards,
Julián

Re: I2S data transfer via DMA

Mohit_Manvar — Mon, 12 Feb 2024 04:00:52 GMT

Hi,
I'm using RTM 4.0.3 for example projects along with S32Design studio v3.4.
I want to transfer data over DMA but don't know what to be configured exactly.

Need small helping reply.

Mohit

Re: I2S data transfer via DMA

Julián_AragónM — Mon, 12 Feb 2024 20:51:06 GMT

Hi @Mohit_Manvar,

You can look into the I2S Example included in the RTD 4.0.0:

The configuration requires for the DMA module has to be initialized prior to usage in DMA mode, as well as being allocated by the application.

In interrupt mode, if mux line is enabled then user must turn on only one bit in ChannelEnable, which will be the data line to output data. Number of data buffers to be muxed is specified in ChannelCount field.

In DMA mode, if mux line is enabled then user must turn on number of bits equal to number of data buffers to be muxed. The data lines corresponding to these bits will output the same as each other.

Also in DMA mode, if a mux mode is selected, ChannelEnable must be turned on from bit 0, and immediately aboves (for example turning on bit 0 and bit 2 is not a correct configuration).

You can find some pointers for I2S FlexIO DMA transfer in this community post: S32K3 S32DS3.5 I2S demo by FlexIO with DMA - NXP Community

Best regards,
Julián

Re: I2S data transfer via DMA

Mohit_Manvar — Wed, 14 Feb 2024 06:37:51 GMT

hi,

As I already mentioned that I'm not using RTD. I'm using RTM so I have limited options of examples.

also in parallel can you check for bare-metal code to transmit data via I2S over DMA?

I already gone through following examples but didn't find anything helpful.

Mohit

Re: I2S data transfer via DMA

Julián_AragónM — Wed, 14 Feb 2024 23:57:35 GMT

Hi @Mohit_Manvar,

I apologize for the misunderstanding. Using RTM you can look inside the Design Studio folder path:

C:\NXP\S32DS.3.4\S32DS\software\S32SDK_S32K1XX_RTM_4.0.3\doc

You can look into chapter 16.53 FlexIO I2S Driver where some important notes are explained.

"This driver needs two DMA channels for its operation when it is initialized in DMA mode. The DMA channels must be initialized by the application before initializing the driver. Refer to EDMA driver for DMA channels initialization."

Please look into the document for more notes and pointers to implement the DMA and both Master/Slave for the I2S driver.

You can also take the flexio_i2s_master/slave examples from the RTM:

You can refer to the EDMA driver for DMA channel initializations.

Best regards,
Julián

Re: I2S data transfer via DMA

Mohit_Manvar — Tue, 20 Feb 2024 04:09:30 GMT

Hello,

Somehow I figured out use of DMA in RTM. currently I'm facing issue of phase drift like two waveforms should be phase aligned.

I'm using FlexIo I2S for SCLk and LRCK and flexio's time and shifters (not FTM) to generate MCLK. but MCLK is not aligning with LRCK.below are some requirement and snapshots.

Requirement of waveform alignment:

Current waveforms generated:

(we are facing 10ns delay in clocks)

we need solution to generate all clocks on same time and it should generate continuous once we enable them.

Regards,
Mohit

Re: I2S data transfer via DMA

Julián_AragónM — Wed, 21 Feb 2024 20:26:54 GMT

Hi @Mohit_Manvar,

Could you share your configuration for I2S timers and shifters?

You can use as reference the following application note for communication emulation and timing peripherals using FlexIO: AN12174: Using FlexIO to emulate communications and timing peripherals.

Section 7 describes how to emulate I2S bus Master, as well as some configurations for shifters and timers.

Best regards,
Julián.