<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32 SDK中的主题 To set the RTR bit in Rx buffer in s32k144</title>
    <link>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640329#M3052</link>
    <description>&lt;P&gt;Hi ,I have doubt in RTR that how to set the RTR&amp;nbsp; bit in s32k144 and how to receive the RTR request and sent response? can u kindly help me in this.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;void FLEXCAN0_init(void) {&lt;BR /&gt;#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */&lt;BR /&gt;uint32_t i=0;&lt;/P&gt;&lt;P&gt;PCC-&amp;gt;PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */&lt;/P&gt;&lt;P&gt;CAN0-&amp;gt;MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */&lt;BR /&gt;CAN0-&amp;gt;CTRL1 &amp;amp;= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;CAN0-&amp;gt;MCR &amp;amp;= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/&lt;BR /&gt;while (!((CAN0-&amp;gt;MCR &amp;amp; CAN_MCR_FRZACK_MASK) &amp;gt;&amp;gt; CAN_MCR_FRZACK_SHIFT)) {}&lt;BR /&gt;/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */&lt;BR /&gt;CAN0-&amp;gt;CTRL1 = 0x00DB0006; /* Configure for 500 KHz bit time */&lt;BR /&gt;/* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */&lt;BR /&gt;/* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */&lt;BR /&gt;/* so PRESDIV = 0 */&lt;BR /&gt;/* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */&lt;BR /&gt;/* PSEG1 = PSEG2 = 3 */&lt;BR /&gt;/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */&lt;BR /&gt;/* RJW: since Phase_Seg2 &amp;gt;=4, RJW+1=4 so RJW=3. */&lt;BR /&gt;/* SMP = 1: use 3 bits per CAN sample */&lt;BR /&gt;/* CLKSRC=0 (unchanged): Fcanclk= Fosc= 8 MHz */&lt;BR /&gt;for(i=0; i&amp;lt;128; i++ ) { /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words*/&lt;BR /&gt;CAN0-&amp;gt;RAMn[i] = 0; /* Clear msg buf word */&lt;BR /&gt;}&lt;BR /&gt;for(i=0; i&amp;lt;16; i++ ) { /* In FRZ mode, init CAN0 16 msg buf filters */&lt;BR /&gt;CAN0-&amp;gt;RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */&lt;BR /&gt;}&lt;BR /&gt;CAN0-&amp;gt;RXMGMASK = 0xFFFFFFFF; /* Global acceptance mask: check all ID bits */&lt;/P&gt;&lt;P&gt;// CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C400000 | 8 &amp;lt;&amp;lt;CAN_WMBn_CS_DLC_SHIFT;&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /*0000 0100 0101 0000 0000 0000 0000 0000 Msg Buf 4, word 0: Enable for reception */&lt;BR /&gt;/* EDL,BRS,ESI=0: CANFD not used */&lt;BR /&gt;/* CODE=4: MB set to RX inactive */&lt;BR /&gt;/* IDE=0: Standard ID */&lt;BR /&gt;/* SRR, RTR, TIME STAMP = 0: not applicable */&lt;BR /&gt;// CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C500000 | 8 &amp;lt;&amp;lt;CAN_WMBn_CS_DLC_SHIFT;&lt;BR /&gt;#ifdef NODE_A /* Node A receives msg with std ID 0x511 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */&lt;BR /&gt;#else /* Node B to receive msg with std ID 0x555 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] = 0x15540000; /* Msg Buf 4, word 1: Standard ID = 0x555 */&lt;BR /&gt;#endif&lt;BR /&gt;/* PRIO = 0: CANFD not used */&lt;BR /&gt;CAN0-&amp;gt;MCR = 0x0000001F; /* Negate FlexCAN 1 halt state for 32 MBs */&lt;BR /&gt;while ((CAN0-&amp;gt;MCR &amp;amp;&amp;amp; CAN_MCR_FRZACK_MASK) &amp;gt;&amp;gt; CAN_MCR_FRZACK_SHIFT) {}&lt;BR /&gt;/* Good practice: wait for FRZACK to clear (not in freeze mode) */&lt;BR /&gt;while ((CAN0-&amp;gt;MCR &amp;amp;&amp;amp; CAN_MCR_NOTRDY_MASK) &amp;gt;&amp;gt; CAN_MCR_NOTRDY_SHIFT) {}&lt;BR /&gt;/* Good practice: wait for NOTRDY to clear (module ready) */&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;void FLEXCAN0_transmit_msg(uint32_t sndId,uint8_t *pdata) { /* Assumption: Message buffer CODE is INACTIVE */&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;CAN0-&amp;gt;IFLAG1 = 0x00000001; /* Clear CAN 0 MB 0 flag without clearing others*/&lt;/P&gt;&lt;P&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 2] = 0xA5112233; /* MB0 word 2: data word 0 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 3] = 0x44556677; /* MB0 word 3: data word 1 */&lt;/P&gt;&lt;P&gt;#ifdef NODE_A&lt;BR /&gt;// CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 1] = 0x15540000; /* MB0 word 1: Tx msg with STD ID 0x555 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 1] = sndId &amp;lt;&amp;lt; 18; /* MB0 word 1: Tx msg with STD ID 0x555 */&lt;BR /&gt;#else&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 1] = 0x14440000; /* MB0 word 1: Tx msg with STD ID 0x511 */&lt;BR /&gt;#endif&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C400000 | 8 &amp;lt;&amp;lt;CAN_WMBn_CS_DLC_SHIFT; /* MB0 word 0: */&lt;BR /&gt;/* EDL,BRS,ESI=0: CANFD not used */&lt;BR /&gt;/* CODE=0xC: Activate msg buf to transmit */&lt;BR /&gt;/* IDE=0: Standard ID */&lt;BR /&gt;/* SRR=1 Tx frame (not req'd for std ID) */&lt;BR /&gt;/* RTR = 0: data, not remote tx request frame*/&lt;BR /&gt;/* DLC = 8 bytes */&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;void FLEXCAN0_receive_msg(uint8_t newDat[8],uint32_t * msgId) { /* Receive msg from ID 0x556 using msg buffer 4 */&lt;BR /&gt;uint8_t j;&lt;BR /&gt;uint32_t dummy;&lt;/P&gt;&lt;P&gt;RxCODE = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] &amp;amp; 0x07000000) &amp;gt;&amp;gt; 24; /* Read CODE field */&lt;BR /&gt;// RxID = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] &amp;amp; CAN_WMBn_ID_ID_MASK) &amp;gt;&amp;gt; CAN_WMBn_ID_ID_SHIFT ;&lt;BR /&gt;*msgId =((CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] &amp;amp; 0x1ffc0000UL) &amp;gt;&amp;gt; 18) ;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RxLENGTH = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] &amp;amp; CAN_WMBn_CS_DLC_MASK)&amp;gt;&amp;gt;CAN_WMBn_CS_DLC_SHIFT ;&lt;/P&gt;&lt;P&gt;// RxLENGTH = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] &amp;amp; CAN_WMBn_CS_DLC_MASK) &amp;gt;&amp;gt;CAN_WMBn_CS_DLC_MASK ;&lt;/P&gt;&lt;P&gt;for (j=0; j&amp;lt;2; j++) { /* Read two words of data (8 bytes) */&lt;BR /&gt;RxDATA[j] = CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 2 + j];&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;RxTIMESTAMP = (CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] &amp;amp; 0x000FFFF);&lt;BR /&gt;dummy = CAN0-&amp;gt;TIMER; /* Read TIMER to unlock message buffers */&lt;BR /&gt;CAN0-&amp;gt;IFLAG1 = 0x00000010; /* Clear CAN 0 MB 4 flag without clearing others*/&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 26 Apr 2023 07:47:07 GMT</pubDate>
    <dc:creator>sathyamoorthy</dc:creator>
    <dc:date>2023-04-26T07:47:07Z</dc:date>
    <item>
      <title>To set the RTR bit in Rx buffer in s32k144</title>
      <link>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640329#M3052</link>
      <description>&lt;P&gt;Hi ,I have doubt in RTR that how to set the RTR&amp;nbsp; bit in s32k144 and how to receive the RTR request and sent response? can u kindly help me in this.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;void FLEXCAN0_init(void) {&lt;BR /&gt;#define MSG_BUF_SIZE 4 /* Msg Buffer Size. (CAN 2.0AB: 2 hdr + 2 data= 4 words) */&lt;BR /&gt;uint32_t i=0;&lt;/P&gt;&lt;P&gt;PCC-&amp;gt;PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */&lt;/P&gt;&lt;P&gt;CAN0-&amp;gt;MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */&lt;BR /&gt;CAN0-&amp;gt;CTRL1 &amp;amp;= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;CAN0-&amp;gt;MCR &amp;amp;= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/&lt;BR /&gt;while (!((CAN0-&amp;gt;MCR &amp;amp; CAN_MCR_FRZACK_MASK) &amp;gt;&amp;gt; CAN_MCR_FRZACK_SHIFT)) {}&lt;BR /&gt;/* Good practice: wait for FRZACK=1 on freeze mode entry/exit */&lt;BR /&gt;CAN0-&amp;gt;CTRL1 = 0x00DB0006; /* Configure for 500 KHz bit time */&lt;BR /&gt;/* Time quanta freq = 16 time quanta x 500 KHz bit time= 8MHz */&lt;BR /&gt;/* PRESDIV+1 = Fclksrc/Ftq = 8 MHz/8 MHz = 1 */&lt;BR /&gt;/* so PRESDIV = 0 */&lt;BR /&gt;/* PSEG2 = Phase_Seg2 - 1 = 4 - 1 = 3 */&lt;BR /&gt;/* PSEG1 = PSEG2 = 3 */&lt;BR /&gt;/* PROPSEG= Prop_Seg - 1 = 7 - 1 = 6 */&lt;BR /&gt;/* RJW: since Phase_Seg2 &amp;gt;=4, RJW+1=4 so RJW=3. */&lt;BR /&gt;/* SMP = 1: use 3 bits per CAN sample */&lt;BR /&gt;/* CLKSRC=0 (unchanged): Fcanclk= Fosc= 8 MHz */&lt;BR /&gt;for(i=0; i&amp;lt;128; i++ ) { /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words*/&lt;BR /&gt;CAN0-&amp;gt;RAMn[i] = 0; /* Clear msg buf word */&lt;BR /&gt;}&lt;BR /&gt;for(i=0; i&amp;lt;16; i++ ) { /* In FRZ mode, init CAN0 16 msg buf filters */&lt;BR /&gt;CAN0-&amp;gt;RXIMR[i] = 0xFFFFFFFF; /* Check all ID bits for incoming messages */&lt;BR /&gt;}&lt;BR /&gt;CAN0-&amp;gt;RXMGMASK = 0xFFFFFFFF; /* Global acceptance mask: check all ID bits */&lt;/P&gt;&lt;P&gt;// CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C400000 | 8 &amp;lt;&amp;lt;CAN_WMBn_CS_DLC_SHIFT;&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] = 0x04000000; /*0000 0100 0101 0000 0000 0000 0000 0000 Msg Buf 4, word 0: Enable for reception */&lt;BR /&gt;/* EDL,BRS,ESI=0: CANFD not used */&lt;BR /&gt;/* CODE=4: MB set to RX inactive */&lt;BR /&gt;/* IDE=0: Standard ID */&lt;BR /&gt;/* SRR, RTR, TIME STAMP = 0: not applicable */&lt;BR /&gt;// CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C500000 | 8 &amp;lt;&amp;lt;CAN_WMBn_CS_DLC_SHIFT;&lt;BR /&gt;#ifdef NODE_A /* Node A receives msg with std ID 0x511 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */&lt;BR /&gt;#else /* Node B to receive msg with std ID 0x555 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] = 0x15540000; /* Msg Buf 4, word 1: Standard ID = 0x555 */&lt;BR /&gt;#endif&lt;BR /&gt;/* PRIO = 0: CANFD not used */&lt;BR /&gt;CAN0-&amp;gt;MCR = 0x0000001F; /* Negate FlexCAN 1 halt state for 32 MBs */&lt;BR /&gt;while ((CAN0-&amp;gt;MCR &amp;amp;&amp;amp; CAN_MCR_FRZACK_MASK) &amp;gt;&amp;gt; CAN_MCR_FRZACK_SHIFT) {}&lt;BR /&gt;/* Good practice: wait for FRZACK to clear (not in freeze mode) */&lt;BR /&gt;while ((CAN0-&amp;gt;MCR &amp;amp;&amp;amp; CAN_MCR_NOTRDY_MASK) &amp;gt;&amp;gt; CAN_MCR_NOTRDY_SHIFT) {}&lt;BR /&gt;/* Good practice: wait for NOTRDY to clear (module ready) */&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;void FLEXCAN0_transmit_msg(uint32_t sndId,uint8_t *pdata) { /* Assumption: Message buffer CODE is INACTIVE */&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;CAN0-&amp;gt;IFLAG1 = 0x00000001; /* Clear CAN 0 MB 0 flag without clearing others*/&lt;/P&gt;&lt;P&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 2] = 0xA5112233; /* MB0 word 2: data word 0 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 3] = 0x44556677; /* MB0 word 3: data word 1 */&lt;/P&gt;&lt;P&gt;#ifdef NODE_A&lt;BR /&gt;// CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 1] = 0x15540000; /* MB0 word 1: Tx msg with STD ID 0x555 */&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 1] = sndId &amp;lt;&amp;lt; 18; /* MB0 word 1: Tx msg with STD ID 0x555 */&lt;BR /&gt;#else&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 1] = 0x14440000; /* MB0 word 1: Tx msg with STD ID 0x511 */&lt;BR /&gt;#endif&lt;BR /&gt;CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] = 0x0C400000 | 8 &amp;lt;&amp;lt;CAN_WMBn_CS_DLC_SHIFT; /* MB0 word 0: */&lt;BR /&gt;/* EDL,BRS,ESI=0: CANFD not used */&lt;BR /&gt;/* CODE=0xC: Activate msg buf to transmit */&lt;BR /&gt;/* IDE=0: Standard ID */&lt;BR /&gt;/* SRR=1 Tx frame (not req'd for std ID) */&lt;BR /&gt;/* RTR = 0: data, not remote tx request frame*/&lt;BR /&gt;/* DLC = 8 bytes */&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;void FLEXCAN0_receive_msg(uint8_t newDat[8],uint32_t * msgId) { /* Receive msg from ID 0x556 using msg buffer 4 */&lt;BR /&gt;uint8_t j;&lt;BR /&gt;uint32_t dummy;&lt;/P&gt;&lt;P&gt;RxCODE = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] &amp;amp; 0x07000000) &amp;gt;&amp;gt; 24; /* Read CODE field */&lt;BR /&gt;// RxID = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] &amp;amp; CAN_WMBn_ID_ID_MASK) &amp;gt;&amp;gt; CAN_WMBn_ID_ID_SHIFT ;&lt;BR /&gt;*msgId =((CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 1] &amp;amp; 0x1ffc0000UL) &amp;gt;&amp;gt; 18) ;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;RxLENGTH = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] &amp;amp; CAN_WMBn_CS_DLC_MASK)&amp;gt;&amp;gt;CAN_WMBn_CS_DLC_SHIFT ;&lt;/P&gt;&lt;P&gt;// RxLENGTH = (CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 0] &amp;amp; CAN_WMBn_CS_DLC_MASK) &amp;gt;&amp;gt;CAN_WMBn_CS_DLC_MASK ;&lt;/P&gt;&lt;P&gt;for (j=0; j&amp;lt;2; j++) { /* Read two words of data (8 bytes) */&lt;BR /&gt;RxDATA[j] = CAN0-&amp;gt;RAMn[ 4*MSG_BUF_SIZE + 2 + j];&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;RxTIMESTAMP = (CAN0-&amp;gt;RAMn[ 0*MSG_BUF_SIZE + 0] &amp;amp; 0x000FFFF);&lt;BR /&gt;dummy = CAN0-&amp;gt;TIMER; /* Read TIMER to unlock message buffers */&lt;BR /&gt;CAN0-&amp;gt;IFLAG1 = 0x00000010; /* Clear CAN 0 MB 4 flag without clearing others*/&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 26 Apr 2023 07:47:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640329#M3052</guid>
      <dc:creator>sathyamoorthy</dc:creator>
      <dc:date>2023-04-26T07:47:07Z</dc:date>
    </item>
    <item>
      <title>Re: To set the RTR bit in Rx buffer in s32k144</title>
      <link>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640448#M3054</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;please refer to chapter&amp;nbsp;55.3.10.4 Remote frames of the device RM.&lt;/P&gt;&lt;P&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Wed, 26 Apr 2023 09:48:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640448#M3054</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-04-26T09:48:04Z</dc:date>
    </item>
    <item>
      <title>Re: To set the RTR bit in Rx buffer in s32k144</title>
      <link>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640562#M3056</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;hi,&lt;/P&gt;&lt;P&gt;Do you have any sample code to set RTR bit in Rx buffer.&lt;/P&gt;</description>
      <pubDate>Wed, 26 Apr 2023 11:58:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1640562#M3056</guid>
      <dc:creator>sathyamoorthy</dc:creator>
      <dc:date>2023-04-26T11:58:33Z</dc:date>
    </item>
    <item>
      <title>Re: To set the RTR bit in Rx buffer in s32k144</title>
      <link>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1641526#M3059</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;if you want to configure an MB to recognize remote request frame and send a response automatically to that, then simply fill the MB with matching ID and required payload to be sent. Then set the MB's CODE field to 0xA.&lt;/P&gt;
&lt;P&gt;If you want to send remote request frame just set RTR bit of the MB and then set MB's CODE to 0xC.&lt;BR /&gt;&lt;BR /&gt;BR, Petr&lt;/P&gt;</description>
      <pubDate>Thu, 27 Apr 2023 11:19:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/To-set-the-RTR-bit-in-Rx-buffer-in-s32k144/m-p/1641526#M3059</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2023-04-27T11:19:21Z</dc:date>
    </item>
  </channel>
</rss>

