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    <title>S32 SDKのトピックS32K148 LPSPI transfer error</title>
    <link>https://community.nxp.com/t5/S32-SDK/S32K148-LPSPI-transfer-error/m-p/1446396#M2503</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Hi NXP community,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have a problem with the LPSPI0 transfers which explain below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;When I set LPSPI0 as master to transmit 4 bytes at 4,8MBaudrate with LPSPI0_CLK_SEL = 24MHz (FIRCDIV2 / 2), there seems to be a pause in the middle of the 4 bytes I’m sending.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Inkedphoto5870704704739195328_LI.jpg" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177478i9463887057136707/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Inkedphoto5870704704739195328_LI.jpg" alt="Inkedphoto5870704704739195328_LI.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The applied settings can be seen in the following images.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="a.JPG" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177479i5863A6AEF88C243E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="a.JPG" alt="a.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;To isolate the problem as much as possible I have done a project that only sets LPSPI0 as master and makes an infinite loop that only makes transmissions and waits.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If you need to clarify anything about the management or configuration I do in the LPSPI interface, please let me know.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;</description>
    <pubDate>Wed, 20 Apr 2022 12:05:45 GMT</pubDate>
    <dc:creator>FBS</dc:creator>
    <dc:date>2022-04-20T12:05:45Z</dc:date>
    <item>
      <title>S32K148 LPSPI transfer error</title>
      <link>https://community.nxp.com/t5/S32-SDK/S32K148-LPSPI-transfer-error/m-p/1446396#M2503</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi NXP community,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have a problem with the LPSPI0 transfers which explain below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;When I set LPSPI0 as master to transmit 4 bytes at 4,8MBaudrate with LPSPI0_CLK_SEL = 24MHz (FIRCDIV2 / 2), there seems to be a pause in the middle of the 4 bytes I’m sending.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Inkedphoto5870704704739195328_LI.jpg" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177478i9463887057136707/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Inkedphoto5870704704739195328_LI.jpg" alt="Inkedphoto5870704704739195328_LI.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;The applied settings can be seen in the following images.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="a.JPG" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177479i5863A6AEF88C243E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="a.JPG" alt="a.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;To isolate the problem as much as possible I have done a project that only sets LPSPI0 as master and makes an infinite loop that only makes transmissions and waits.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If you need to clarify anything about the management or configuration I do in the LPSPI interface, please let me know.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;</description>
      <pubDate>Wed, 20 Apr 2022 12:05:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/S32K148-LPSPI-transfer-error/m-p/1446396#M2503</guid>
      <dc:creator>FBS</dc:creator>
      <dc:date>2022-04-20T12:05:45Z</dc:date>
    </item>
    <item>
      <title>Re: S32K148 LPSPI transfer error</title>
      <link>https://community.nxp.com/t5/S32-SDK/S32K148-LPSPI-transfer-error/m-p/1447222#M2506</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/198056"&gt;@FBS&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;If you configure the SDK LPSPI for 8bit frames, in the interrupt mode, the LPSPI_DRV_FillupTxBuffer()&amp;nbsp;function (lpspi_shared_function.c) that is called from the interrupt handler can fill the TX FIFO with 8bit frames. The FIFO can take only up to 4 such frames.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1650540747264.png" style="width: 734px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177613iC5B8B5449C15E2C8/image-dimensions/734x587?v=v2" width="734" height="587" role="button" title="danielmartynek_0-1650540747264.png" alt="danielmartynek_0-1650540747264.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The SDK LPSPI driver needs some time to fill the TX FIFO (CPU overhead).&lt;/P&gt;
&lt;P&gt;You can reduce the delay either by increasing the system clock frequency or by reducing the SPI bitrate.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 21 Apr 2022 11:35:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/S32K148-LPSPI-transfer-error/m-p/1447222#M2506</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2022-04-21T11:35:09Z</dc:date>
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