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    <title>S32 SDK中的主题 Re: Questions about FlexRAM</title>
    <link>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1149533#M1863</link>
    <description>&lt;P&gt;Hello Phillip,&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;A1&lt;/P&gt;
&lt;P&gt;Please refer to the RM, rev.12.1,&amp;nbsp;Section 31.3.2 SRAM accessibility&lt;/P&gt;
&lt;P&gt;"To supplement the main system RAM, FlexRAM can be used as system RAM. However,&lt;BR /&gt;FlexRAM accesses involve additional system latencies."&lt;/P&gt;
&lt;P&gt;This is because FlexRAM is not tightly coupled with the core.&lt;/P&gt;
&lt;P&gt;As you can see below, the FlexRAM is a slave on the Crossbar switch.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1599463845985.png" style="width: 529px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124488iE9FA7BB2F8559446/image-dimensions/529x503?v=v2" width="529" height="503" role="button" title="danielmartynek_0-1599463845985.png" alt="danielmartynek_0-1599463845985.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;The SRAM_L and SRAM_U regions are contiguous, mapped right next to each other.&lt;/P&gt;
&lt;P&gt;But FlexRAM starts at 0x14000000.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_1-1599464169821.png" style="width: 690px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124489i6845BFFF5B94F322/image-dimensions/690x245?v=v2" width="690" height="245" role="button" title="danielmartynek_1-1599464169821.png" alt="danielmartynek_1-1599464169821.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;A2.&lt;/P&gt;
&lt;P&gt;That simply means that the FlexRAM is initialized with all ones, like each 32b word is written with 0xFFFFFFFF.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
    <pubDate>Mon, 07 Sep 2020 07:45:43 GMT</pubDate>
    <dc:creator>danielmartynek</dc:creator>
    <dc:date>2020-09-07T07:45:43Z</dc:date>
    <item>
      <title>Questions about FlexRAM</title>
      <link>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1142975#M1852</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;I'm using S32k144.&lt;/P&gt;&lt;P&gt;I got two questions studying&amp;nbsp; EEE&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. FlexRAM is slower than SRAM&lt;/P&gt;&lt;DIV class="mceNonEditable lia-copypaste-placeholder"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;Please see this picture&amp;nbsp;. (it's from AN11983 p11)&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="help.PNG" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124301i9FAF40C11A120B3A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="help.PNG" alt="help.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;When I see flash memory map, I think FlexRAM is also contiguous addresses.&lt;/P&gt;&lt;P&gt;but this is saying non-contiguous...&lt;/P&gt;&lt;P&gt;and is that why the FlexRAM is slower than SRAM?&lt;/P&gt;&lt;P&gt;FlexRAM is not static RAM?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. "a background pattern of all ones" ???&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="help2.PNG" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124302iE3A7B9F638063728/image-size/medium?v=v2&amp;amp;px=400" role="button" title="help2.PNG" alt="help2.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;I saw&amp;nbsp;"a background pattern of all ones" several times in NXP documents..&lt;/P&gt;&lt;P&gt;But I have no idea what it means since I'm not native English speaker,,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt; &lt;/P&gt;&lt;P&gt;Please explain to me&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Phillip&lt;/P&gt;</description>
      <pubDate>Fri, 04 Sep 2020 01:08:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1142975#M1852</guid>
      <dc:creator>kmh48301</dc:creator>
      <dc:date>2020-09-04T01:08:59Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about FlexRAM</title>
      <link>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1149533#M1863</link>
      <description>&lt;P&gt;Hello Phillip,&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;A1&lt;/P&gt;
&lt;P&gt;Please refer to the RM, rev.12.1,&amp;nbsp;Section 31.3.2 SRAM accessibility&lt;/P&gt;
&lt;P&gt;"To supplement the main system RAM, FlexRAM can be used as system RAM. However,&lt;BR /&gt;FlexRAM accesses involve additional system latencies."&lt;/P&gt;
&lt;P&gt;This is because FlexRAM is not tightly coupled with the core.&lt;/P&gt;
&lt;P&gt;As you can see below, the FlexRAM is a slave on the Crossbar switch.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_0-1599463845985.png" style="width: 529px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124488iE9FA7BB2F8559446/image-dimensions/529x503?v=v2" width="529" height="503" role="button" title="danielmartynek_0-1599463845985.png" alt="danielmartynek_0-1599463845985.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;The SRAM_L and SRAM_U regions are contiguous, mapped right next to each other.&lt;/P&gt;
&lt;P&gt;But FlexRAM starts at 0x14000000.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="danielmartynek_1-1599464169821.png" style="width: 690px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124489i6845BFFF5B94F322/image-dimensions/690x245?v=v2" width="690" height="245" role="button" title="danielmartynek_1-1599464169821.png" alt="danielmartynek_1-1599464169821.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;A2.&lt;/P&gt;
&lt;P&gt;That simply means that the FlexRAM is initialized with all ones, like each 32b word is written with 0xFFFFFFFF.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Daniel&lt;/P&gt;</description>
      <pubDate>Mon, 07 Sep 2020 07:45:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1149533#M1863</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2020-09-07T07:45:43Z</dc:date>
    </item>
    <item>
      <title>Re: Questions about FlexRAM</title>
      <link>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1149877#M1865</link>
      <description>&lt;P&gt;Thanks Daniel. I understood.&lt;/P&gt;</description>
      <pubDate>Mon, 07 Sep 2020 23:13:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/Questions-about-FlexRAM/m-p/1149877#M1865</guid>
      <dc:creator>kmh48301</dc:creator>
      <dc:date>2020-09-07T23:13:55Z</dc:date>
    </item>
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