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    <title>topic CSEc PRAM Command Header Function format in S32 SDK</title>
    <link>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1134743#M1841</link>
    <description>&lt;P&gt;Hi, all!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have question about CSEc PRAM Command Header.&lt;/P&gt;&lt;P&gt;There is 'FuncFormat' that specifies 'how the data is transferred to/from the CSEc'.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In AN5401, there is this explanation.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="skseofh_1-1599092331657.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124126i40EA8583B447FF83/image-size/medium?v=v2&amp;amp;px=400" role="button" title="skseofh_1-1599092331657.png" alt="skseofh_1-1599092331657.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I can't understand 'the main core or DMA' part.&lt;/P&gt;&lt;P&gt;Where exactly does this part point?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I think 'the main core or DMA' point 'RAM(FTFC Core)' in figure below(AN5401).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="skseofh_2-1599092765570.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124127iE73EE9435F63C3A5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="skseofh_2-1599092765570.png" alt="skseofh_2-1599092765570.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If so, which address is 'RAM(FTFC Core)' in the memory map?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 03 Sep 2020 00:31:35 GMT</pubDate>
    <dc:creator>skseofh</dc:creator>
    <dc:date>2020-09-03T00:31:35Z</dc:date>
    <item>
      <title>CSEc PRAM Command Header Function format</title>
      <link>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1134743#M1841</link>
      <description>&lt;P&gt;Hi, all!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have question about CSEc PRAM Command Header.&lt;/P&gt;&lt;P&gt;There is 'FuncFormat' that specifies 'how the data is transferred to/from the CSEc'.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In AN5401, there is this explanation.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="skseofh_1-1599092331657.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124126i40EA8583B447FF83/image-size/medium?v=v2&amp;amp;px=400" role="button" title="skseofh_1-1599092331657.png" alt="skseofh_1-1599092331657.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I can't understand 'the main core or DMA' part.&lt;/P&gt;&lt;P&gt;Where exactly does this part point?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I think 'the main core or DMA' point 'RAM(FTFC Core)' in figure below(AN5401).&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="skseofh_2-1599092765570.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124127iE73EE9435F63C3A5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="skseofh_2-1599092765570.png" alt="skseofh_2-1599092765570.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If so, which address is 'RAM(FTFC Core)' in the memory map?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 03 Sep 2020 00:31:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1134743#M1841</guid>
      <dc:creator>skseofh</dc:creator>
      <dc:date>2020-09-03T00:31:35Z</dc:date>
    </item>
    <item>
      <title>Re: CSEc PRAM Command Header Function format</title>
      <link>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1150526#M1875</link>
      <description>&lt;P&gt;Hello!&lt;/P&gt;
&lt;P&gt;The main core that this part of the document is referring to the MCU core. One of the many functions of the core is transfer information, this transference can be done through the MCU or using the DMA module instead.&lt;/P&gt;
&lt;P&gt;The functionality of the CSE is implemented on the FTFC Core. That RAM is dedicated to the flash controller to improve performance.&lt;/P&gt;
&lt;P&gt;For more detailed information about the memory map, you can find it attached to the s32k1xx reference manual.&lt;/P&gt;
&lt;P&gt;Let me know if this is helpful, if you have more questions do not hesitate to ask me. &lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Omar&lt;/P&gt;</description>
      <pubDate>Tue, 08 Sep 2020 18:33:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1150526#M1875</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2020-09-08T18:33:39Z</dc:date>
    </item>
    <item>
      <title>Re: CSEc PRAM Command Header Function format</title>
      <link>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1151193#M1881</link>
      <description>&lt;P&gt;I checked the memory map and there is this sheet.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="skseofh_0-1599702203000.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/124786i1AB8255DEA59EB7F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="skseofh_0-1599702203000.png" alt="skseofh_0-1599702203000.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm not sure which part is MCU core and DMA.&lt;/P&gt;&lt;P&gt;Could you explain more please?&lt;/P&gt;</description>
      <pubDate>Thu, 10 Sep 2020 01:44:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1151193#M1881</guid>
      <dc:creator>skseofh</dc:creator>
      <dc:date>2020-09-10T01:44:55Z</dc:date>
    </item>
    <item>
      <title>Re: CSEc PRAM Command Header Function format</title>
      <link>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1153616#M1911</link>
      <description>&lt;P&gt;Hello &lt;SPAN class="UserName lia-user-name lia-user-rank-Contributor-II lia-component-message-view-widget-author-username"&gt;&lt;A id="link_12" class="lia-link-navigation lia-page-link lia-user-name-link" style="color: #333f48;" href="https://community.nxp.com/t5/user/viewprofilepage/user-id/159519" target="_self"&gt;&lt;SPAN class=""&gt;skseofh&lt;/SPAN&gt;&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I will gladly answer your question. The MCU core refers to the ARM Cortex. The core can transfer data. The DMA is a module capable of transfer blocks of data without the core intervention.&lt;/P&gt;
&lt;P&gt;Let me know if this is helpful, if you have more questions do not hesitate to ask me.&lt;/P&gt;</description>
      <pubDate>Tue, 15 Sep 2020 17:39:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-SDK/CSEc-PRAM-Command-Header-Function-format/m-p/1153616#M1911</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2020-09-15T17:39:56Z</dc:date>
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