<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S32 Design StudioのトピックRe: RAM segments merging</title>
    <link>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/1310231#M7652</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am working on S3k148 controller and faced the similar issue. I required more .bss section so modified the linker file accordingly.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Existing RAM split-up:&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_L */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x1FFE0000, LENGTH = 0x00020000&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_U */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data_2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x20000000, LENGTH = 0x0001F000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Modified:&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_L */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x1FFE0000, LENGTH = 0x0003F000-0x2000&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_U */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data_2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x2001D000, LENGTH = 0x00002000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have enclosed the complete linker file for your reference. The memory consumtion in bss in crossing the boundary region and still I did not face any issue of &lt;STRONG&gt;hard fault&lt;/STRONG&gt;.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can I know the reason for hard fault not occurring. Looking at the above comments, I am supposed to get "Hard Fault" which has reduced my confidence level.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please advice.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hemadri&lt;/P&gt;</description>
    <pubDate>Tue, 20 Jul 2021 06:46:17 GMT</pubDate>
    <dc:creator>hemadri_payam</dc:creator>
    <dc:date>2021-07-20T06:46:17Z</dc:date>
    <item>
      <title>RAM segments merging</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802147#M3411</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;S32K14x devices have 2 RAM regions named SRAM_U and SRAM_L. They are arranged in continuous manner. E.g.: S32K142 has the following RAM regions: 1FFF_C000 to 1FFF_FFFF and 2000_0000 to 2000_2FFF.&lt;/P&gt;&lt;P&gt;The linker scripts shipped with an SDK has separate memory segments for them:&lt;/P&gt;&lt;PRE class="language-none line-numbers"&gt;&lt;CODE&gt;/* Specify the memory areas */
MEMORY
{
&amp;nbsp; /* SRAM_L */
&amp;nbsp; m_data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x1FFFC000, LENGTH = 0x00004000

&amp;nbsp; /* SRAM_U */
&amp;nbsp; m_data_2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x20000000, LENGTH = 0x00003000
}&lt;SPAN class="line-numbers-rows"&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;m_data is used to store code that should be in RAM, .data and interrupt vectors.&lt;/P&gt;&lt;P&gt;m_data_2 is used to store .customSection, .bss, heap and stack.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Since there is no gap between the sections, it feels natural to me to merge them into a single segment.&lt;/P&gt;&lt;P&gt;E.g.:&lt;/P&gt;&lt;PRE class="language-none line-numbers"&gt;&lt;CODE&gt;/* Specify the memory areas */
MEMORY
{
&amp;nbsp; /* SRAM_L + SRAM_U */
&amp;nbsp; m_data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x1FFFC000, LENGTH = 0x00007000
}&lt;SPAN class="line-numbers-rows"&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This will make easier to manage big arrays, since you will have single RAM segment.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are there any undesired consequences?&lt;/P&gt;&lt;P&gt;The only undesired consequence I can imagine of is unaligned access on the edge.&lt;/P&gt;&lt;P&gt;E.g.:&lt;/P&gt;&lt;PRE class="language-c line-numbers"&gt;&lt;CODE&gt;&lt;SPAN class="operator token"&gt;*&lt;/SPAN&gt;&lt;SPAN class="punctuation token"&gt;(&lt;/SPAN&gt;int32_t &lt;SPAN class="operator token"&gt;*&lt;/SPAN&gt;&lt;SPAN class="punctuation token"&gt;)&lt;/SPAN&gt;&lt;SPAN class="number token"&gt;0x1FFFFFFF&lt;/SPAN&gt; &lt;SPAN class="operator token"&gt;=&lt;/SPAN&gt; &lt;SPAN class="number token"&gt;42&lt;/SPAN&gt;&lt;SPAN class="punctuation token"&gt;;&lt;/SPAN&gt;&lt;SPAN class="line-numbers-rows"&gt;&lt;SPAN&gt;‍&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/CODE&gt;&lt;/PRE&gt;&lt;P&gt;But such reads/writes should be avoided in any case.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks and regards,&lt;/P&gt;&lt;P&gt;Maksim.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Jul 2018 19:15:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802147#M3411</guid>
      <dc:creator>maksimsalau</dc:creator>
      <dc:date>2018-07-31T19:15:23Z</dc:date>
    </item>
    <item>
      <title>Re: RAM segments merging</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802148#M3412</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, misaligned accesses across that memory boundary will cause a hard fault. There has been a discussion on that topic at the end of the following article:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://mcuoneclipse.com/2013/07/10/freertos-heap-with-segmented-kinetis-k-sram/" title="https://mcuoneclipse.com/2013/07/10/freertos-heap-with-segmented-kinetis-k-sram/"&gt;FreeRTOS Heap with Segmented Kinetis K SRAM&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope that helps,&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Aug 2018 12:05:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802148#M3412</guid>
      <dc:creator>BlackNight</dc:creator>
      <dc:date>2018-08-02T12:05:53Z</dc:date>
    </item>
    <item>
      <title>Re: RAM segments merging</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802149#M3413</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Erich,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks! That helped very much.&lt;/P&gt;&lt;P&gt;I had the very same problem: FreeRTOS heap allocation, so I ended up modifying the linker script to allocate all the regular .bss, .data, interrupt vector table, heap and stack in SRAM_U, and reserve the whole SRAM_L region for FreeRTOS heap.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Maksim.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Aug 2018 12:31:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802149#M3413</guid>
      <dc:creator>maksimsalau</dc:creator>
      <dc:date>2018-08-02T12:31:00Z</dc:date>
    </item>
    <item>
      <title>Re: RAM segments merging</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802150#M3414</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Maksim,&lt;/P&gt;&lt;P&gt;in that case you probably will find that one interesting too:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://mcuoneclipse.com/2017/09/18/using-multiple-memory-regions-with-the-freertos-heap/" title="https://mcuoneclipse.com/2017/09/18/using-multiple-memory-regions-with-the-freertos-heap/"&gt;Using Multiple Memory Regions with the FreeRTOS Heap | MCU on Eclipse&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;That way you can have multiple memory regions used by FreeRTOS.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope this helps,&lt;/P&gt;&lt;P&gt;Erich&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Aug 2018 12:54:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/802150#M3414</guid>
      <dc:creator>BlackNight</dc:creator>
      <dc:date>2018-08-02T12:54:59Z</dc:date>
    </item>
    <item>
      <title>Re: RAM segments merging</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/1310231#M7652</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am working on S3k148 controller and faced the similar issue. I required more .bss section so modified the linker file accordingly.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Existing RAM split-up:&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_L */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x1FFE0000, LENGTH = 0x00020000&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_U */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data_2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x20000000, LENGTH = 0x0001F000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Modified:&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_L */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x1FFE0000, LENGTH = 0x0003F000-0x2000&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* SRAM_U */&lt;/P&gt;&lt;P&gt;&amp;nbsp; m_data_2&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (RW)&amp;nbsp; : ORIGIN = 0x2001D000, LENGTH = 0x00002000&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have enclosed the complete linker file for your reference. The memory consumtion in bss in crossing the boundary region and still I did not face any issue of &lt;STRONG&gt;hard fault&lt;/STRONG&gt;.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can I know the reason for hard fault not occurring. Looking at the above comments, I am supposed to get "Hard Fault" which has reduced my confidence level.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please advice.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hemadri&lt;/P&gt;</description>
      <pubDate>Tue, 20 Jul 2021 06:46:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/RAM-segments-merging/m-p/1310231#M7652</guid>
      <dc:creator>hemadri_payam</dc:creator>
      <dc:date>2021-07-20T06:46:17Z</dc:date>
    </item>
  </channel>
</rss>

