SPI Tx buffer Send

SunW — Tue, 24 Mar 2020 09:45:33 GMT

I want to send SPI buf data;

i do define SPI tx bueffer = {0x03, 0x04,0x05, 0x6};

I saw the example of SPI in S32K

I change SPI buadrate 10MHz.

how do i chage LPSPI1_transmit_16bits_buf ?

I want see example..

/* LPSPI.c (c) 2016 NXP
* Descriptions: S32K144 FlexCAN example functions.
* May 31 2016 S. Mihalik: Initial version.
* Oct 31 2016 SM - adjust PRESCALE for 40 MHz SPLLDIV2_CLK
* Nov 02 2016 SM - cleared flags in transmit, receive functions
*/

#include "S32K144.h" /* include peripheral declarations S32K144 */
#include "LPSPI.h"

void LPSPI1_init_master(void) {
PCC->PCCn[PCC_LPSPI0_INDEX] = 0; /* Disable clocks to modify PCS ( default) */
PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000; /* Enable PCS=SPLL_DIV2 (40 MHz func'l clock) */

LPSPI0->CR    = 0x00000000;   /* Disable module for configuration */
LPSPI0->IER   = 0x00000000;   /* Interrupts not used */
LPSPI0->DER   = 0x00000000;   /* DMA not used */
LPSPI0->CFGR0 = 0x00000000;   /* Defaults: */
                                /* RDM0=0: rec'd data to FIFO as normal */
                                /* CIRFIFO=0; Circular FIFO is disabled */
                                /* HRSEL, HRPOL, HREN=0: Host request disabled */
LPSPI0->CFGR1 = 0x00000001;   /* Configurations: master mode*/
                                /* PCSCFG=0: PCS[3:2] are enabled */
                                /* OUTCFG=0: Output data retains last value when CS negated */
                                /* PINCFG=0: SIN is input, SOUT is output */
                                /* MATCFG=0: Match disabled */
                                /* PCSPOL=0: PCS is active low */
                                /* NOSTALL=0: Stall if Tx FIFO empty or Rx FIFO full */
                                /* AUTOPCS=0: does not apply for master mode */
                                /* SAMPLE=0: input data sampled on SCK edge */
                                /* MASTER=1: Master mode */
LPSPI0->TCR   = 0x4300000F;   /* Transmit cmd: PCS3, 16 bits, prescale func'l clk by 4, etc*/
                                /* CPOL=0: SCK inactive state is low */
                                /* CPHA=1: Change data on SCK lead'g, capture on trail'g edge*/
                                /* PRESCALE=2: Functional clock divided by 2**2 = 4 */
                                /* PCS=3: Transfer using PCS3 */
                                /* LSBF=0: Data is transfered MSB first */
                                /* BYSW=0: Byte swap disabled */
                                /* CONT, CONTC=0: Continuous transfer disabled */
                                /* RXMSK=0: Normal transfer: rx data stored in rx FIFO */
                                /* TXMSK=0: Normal transfer: data loaded from tx FIFO */
                                /* WIDTH=0: Single bit transfer */
                                /* FRAMESZ=15: # bits in frame = 15+1=16 */
LPSPI0->CCR   = 0x04090802;   /* Clock dividers based on prescaled func'l clk of 100 nsec */
                                /* SCKPCS=4: SCK to PCS delay = 4+1 = 5 (500 nsec) */
                                /* PCSSCK=4: PCS to SCK delay = 9+1 = 10 (1 usec) */
                                /* DBT=8: Delay between Transfers = 8+2 = 10 (1 usec) */
                                /* SCKDIV=8: SCK divider =8+2 = 10 (1 usec: 1 MHz baud rate) */
LPSPI0->FCR   = 0x00000003;   /* RXWATER=0: Rx flags set when Rx FIFO >0 */
                                /* TXWATER=3: Tx flags set when Tx FIFO <= 3 */
LPSPI0->CR    = 0x00000009;   /* Enable module for operation */
                                /* DBGEN=1: module enabled in debug mode */
                                /* DOZEN=0: module enabled in Doze mode */
                                /* RST=0: Master logic not reset */
                                /* MEN=1: Module is enabled */
}

void LPSPI1_transmit_16bits (uint16_t send) {
while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = send; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
}

uint16_t LPSPI1_receive_16bits (void) {
uint16_t recieve = 0;

while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
                                   /* Wait at least one RxFIFO entry */
recieve= LPSPI0->RDR;            /* Read received data */
LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */
return recieve;                  /* Return received data */
}

void LPSPI1_transmit_16bits_buf (uint16_t send) {
while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = send; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */
}

Re: SPI Tx buffer Send

dianabatrlova — Thu, 26 Mar 2020 15:33:59 GMT

Hello,

Your baud rate setting is correct.

The reference manual rev 12.1 chapter 51 LPSPI will be useful.

It is up to you how you send data from the buffer.

for example:

void LPSPI1_transmit_16bits_buf (uint16_t buf[])

{

uint32_t i=0;
while(i != 4)

{
LPSPI1_transmit_16bits(buf[i]);
i++;
}
}

If you want to send just 4 bytes you can send the whole array into transmit data register, there is enough space

LPSPI1->TDR = buf[0];
LPSPI1->TDR = buf[1];
LPSPI1->TDR = buf[2];
LPSPI1->TDR = buf[3];

I hope it helps.

Best regards,

Diana

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