topic Re: the question about hared memory between two cores in S32 Design Studio

the question about hared memory between two cores

whagiew — Sat, 26 Jan 2019 04:27:23 GMT

I use the volatile keyword to share the same memory between two cores. When DCache is turned on, the memory values between the two cores are different, and they can only be synchronized when the DCache is turned off.
In the NXP compiler, how is the volatile keyword explained? In addition to turning off DCache or refreshing DCache, is there any other way to synchronize memory data between two? Looking forward to expert guidance, thank you

best regard.

yang

Re: the question about hared memory between two cores

FelipeGarcia — Wed, 30 Jan 2019 20:40:23 GMT

Hi Yang,

Could you please tell me what part are you working on?

Also, it would be useful if you give a little more information about the things you are using in this (IDE, SDK).

Regards,

Felipe

Re: the question about hared memory between two cores

whagiew — Fri, 01 Feb 2019 04:35:52 GMT

Hi Felipe,

I am using s32ds and I am not using the SDK. Under the conditions of turning on and off DCache, use two cores to read and write 0x40000000 of SRAM respectively. And test using "int" type and "volatile int" type respectively. When the DCache is opened, the SRAM is not updated in time in another core.

Best Regards.

Yang

Re: the question about hared memory between two cores

FelipeGarcia — Fri, 01 Feb 2019 17:14:16 GMT

Hi Yang,

Thanks for your reply.

For a better support I'm going to move this thread to the appropriate community space.

Best regards,

Felipe

Re: the question about hared memory between two cores

alexanderfedoto — Fri, 01 Feb 2019 22:14:35 GMT

It would be more helpful if you'll tell which target and what cores do you use.

At first glance Dcache works properly but since there is no cache coherent interconnect between cores you dont see updated value on another core. You have to force write back from cache to memory in this case.

Re: the question about hared memory between two cores

whagiew — Mon, 04 Mar 2019 14:50:05 GMT

Hi,

Thanks for your reply.

I am using S32R274. The two cores are core0(z4) and core2(z7_b).

I want to use key word "volatile" to write through cache, but failed.

I want to know in the NXP compiler, how is the volatile keyword explained? and how can i force write back from cache to memory.

Thanks.

Best regards,

Yang

Re: the question about hared memory between two cores

alexanderfedoto — Tue, 26 Mar 2019 16:02:44 GMT

whagiew@126.com‌

volatile has nothing common with cache. You have to use ppc memory barrier/fence instructions to achieve what you want.

Re: the question about hared memory between two cores

whagiew — Wed, 27 Mar 2019 07:01:58 GMT

Thank you for your reply, I misunderstood the volatile keyword, the cache is actually memory.

thank you.

Best regards.

Yang