<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic S32DS EmbSys registers mixup MPC5746R in S32 Design Studio</title>
    <link>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706113#M1866</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;First off, I really like the EmbSys register view, it's great!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, when configured for MPC5746R with e200 core, there appear to be a few inconsistencies. (See attached embsys1.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. eTPU registers aren't all grouped under eTPU like the other modules. (See attached embsys2.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. eMIOS is confusing and appears to use the wrong addresses? (See attached embsys3.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would expect to see eMIOS1 channel 8 registers cascaded as eMIOS -&amp;gt; eMIOS_1 -&amp;gt; eMIOS_1_UC08 but it seems they are presented as eMIOS -&amp;gt; eMIOS_1_UC08 etc.&lt;/P&gt;&lt;P&gt;Then within each channel, it looks like the other channels are there as well???? (See attached emios2.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now, the addresses...&amp;nbsp; from MPC5746RRM.pdf (See attached emios1.png)&amp;nbsp; I would expect eMIOS1 channel 8 register B to be at:&lt;/P&gt;&lt;P&gt;eMIOS base + channel 8 offset + register B offset&lt;/P&gt;&lt;P&gt;0xFBE64000 + 0x120 + 0x004&lt;/P&gt;&lt;P&gt;= 0xFBE64124&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From MPC5746R.h&lt;/P&gt;&lt;P&gt;#define eMIOS_1 (*(volatile struct eMIOS_tag *) 0xFBE64000UL)&lt;BR /&gt;#define eMIOS_1_UC08 (*(volatile struct eMIOS_tag *) 0xFBE64340UL)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From the ref manual, I thought 0xFBE64340UL is in reserved space?&lt;/P&gt;&lt;P&gt;From the EmbSys view, it thinks that UC08 register B is at 0xFBE64464&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It's also a shame that the register naming has changed from the way MPC563m.h had it. Previously, the channels were referred to using arrays e.g.&lt;/P&gt;&lt;P&gt;EMIOS.CH[8].CBDR.R&lt;/P&gt;&lt;P&gt;now it appears to be:&lt;/P&gt;&lt;P&gt;eMIOS_1.B20.R&lt;/P&gt;&lt;P&gt;without the array and with a definition for each channel.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 13 Oct 2017 13:28:06 GMT</pubDate>
    <dc:creator>jamesmurray</dc:creator>
    <dc:date>2017-10-13T13:28:06Z</dc:date>
    <item>
      <title>S32DS EmbSys registers mixup MPC5746R</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706113#M1866</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;First off, I really like the EmbSys register view, it's great!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, when configured for MPC5746R with e200 core, there appear to be a few inconsistencies. (See attached embsys1.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. eTPU registers aren't all grouped under eTPU like the other modules. (See attached embsys2.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. eMIOS is confusing and appears to use the wrong addresses? (See attached embsys3.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I would expect to see eMIOS1 channel 8 registers cascaded as eMIOS -&amp;gt; eMIOS_1 -&amp;gt; eMIOS_1_UC08 but it seems they are presented as eMIOS -&amp;gt; eMIOS_1_UC08 etc.&lt;/P&gt;&lt;P&gt;Then within each channel, it looks like the other channels are there as well???? (See attached emios2.png)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now, the addresses...&amp;nbsp; from MPC5746RRM.pdf (See attached emios1.png)&amp;nbsp; I would expect eMIOS1 channel 8 register B to be at:&lt;/P&gt;&lt;P&gt;eMIOS base + channel 8 offset + register B offset&lt;/P&gt;&lt;P&gt;0xFBE64000 + 0x120 + 0x004&lt;/P&gt;&lt;P&gt;= 0xFBE64124&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From MPC5746R.h&lt;/P&gt;&lt;P&gt;#define eMIOS_1 (*(volatile struct eMIOS_tag *) 0xFBE64000UL)&lt;BR /&gt;#define eMIOS_1_UC08 (*(volatile struct eMIOS_tag *) 0xFBE64340UL)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From the ref manual, I thought 0xFBE64340UL is in reserved space?&lt;/P&gt;&lt;P&gt;From the EmbSys view, it thinks that UC08 register B is at 0xFBE64464&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It's also a shame that the register naming has changed from the way MPC563m.h had it. Previously, the channels were referred to using arrays e.g.&lt;/P&gt;&lt;P&gt;EMIOS.CH[8].CBDR.R&lt;/P&gt;&lt;P&gt;now it appears to be:&lt;/P&gt;&lt;P&gt;eMIOS_1.B20.R&lt;/P&gt;&lt;P&gt;without the array and with a definition for each channel.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Oct 2017 13:28:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706113#M1866</guid>
      <dc:creator>jamesmurray</dc:creator>
      <dc:date>2017-10-13T13:28:06Z</dc:date>
    </item>
    <item>
      <title>Re: S32DS EmbSys registers mixup MPC5746R</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706114#M1867</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;NXP - any thoughts on this?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 17 Oct 2017 16:54:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706114#M1867</guid>
      <dc:creator>jamesmurray</dc:creator>
      <dc:date>2017-10-17T16:54:07Z</dc:date>
    </item>
    <item>
      <title>Re: S32DS EmbSys registers mixup MPC5746R</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706115#M1868</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;There have been a number of new ARM releases of S32DS. Any chance of showing PowerPC some love and putting out a new release which fixes the bugs I've reported in MPC5746R.h? (eTPU, eMIOS, LINFlex, CAN)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 May 2018 09:50:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706115#M1868</guid>
      <dc:creator>jamesmurray</dc:creator>
      <dc:date>2018-05-30T09:50:44Z</dc:date>
    </item>
    <item>
      <title>Re: S32DS EmbSys registers mixup MPC5746R</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706116#M1869</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi James,&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I already created ticket for your issue last year. I didn't check if the offset mismatch is still present in S32DS Power v2017.R1 with updates. I'll do that.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Jiri&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Jun 2018 11:51:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706116#M1869</guid>
      <dc:creator>jiri_kral</dc:creator>
      <dc:date>2018-06-07T11:51:58Z</dc:date>
    </item>
    <item>
      <title>Re: S32DS EmbSys registers mixup MPC5746R</title>
      <link>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706117#M1870</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Well, the offset mismatch is still present - even with latest update. I'll ping the dev team. Hope the issue will be fixed in next release - the ticket was created during code freeze phase for v2017.R1.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Jiri&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Jun 2018 12:37:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S32-Design-Studio/S32DS-EmbSys-registers-mixup-MPC5746R/m-p/706117#M1870</guid>
      <dc:creator>jiri_kral</dc:creator>
      <dc:date>2018-06-07T12:37:27Z</dc:date>
    </item>
  </channel>
</rss>

