topic Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312 in S32 Design Studio

Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

jacopo_costella — Mon, 09 Oct 2023 09:59:05 GMT

Hello,

with S32DS Ver. 3.4, after running pin and clock configuration of S32K312, I tested a simple program and when entering the function:

Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat (file Clock_Ip_DividerTrigger.c)

the debug session crashed ehwn executing the instruction

DividerStatus = Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK;

Instance = 0;

SelectorIndex = 0.

Do you have any idea?

Thank you very much,

Jacopo

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

danielmartynek — Mon, 09 Oct 2023 13:18:23 GMT

Hi @jacopo_costella,

Is the HSE_FW installed?

Thanks,

BR, Daniel

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

jacopo_costella — Mon, 09 Oct 2023 14:18:13 GMT

Hello Daniel,

thank you very much for your fast feedback. I noticed your suyggestion here;

https://community.nxp.com/t5/S32K/How-to-compile-S32K3-HSE-FW-in-project/m-p/1541925#M18475https://community.nxp.com/t5/S32K/How-to-compile-S32K3-HSE-FW-in-project/td-p/1540212

which demo were you referring to?

Regards,

Jacopo

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

danielmartynek — Tue, 10 Oct 2023 09:41:25 GMT

Hi @jacopo_costella,

Currently, we have some issues with our system, and the demo can't be located at nxp.com.

We are working on it.

All the HSE_FW documentation can be found in the Secure files under an NDA on the S32K3xx webpage though:

https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3

I understand the HSE_FW hasn't been installed on the MCU yet.

Can you share the project so that I can test it?

Thank you,

BR, Daniel

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

jacopo_costella — Tue, 10 Oct 2023 10:18:17 GMT

Hello Daniel,

thank you for your reply.

Please find attached the project.

Have a nice day,

Jacopo

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

danielmartynek — Tue, 10 Oct 2023 12:46:48 GMT

Hi Jacopo,

I don't have this old RTD version installed, so I can't modify and recompile the project.

Anyway, the clock configuration is not correct.

Please set all the clock as per the RM, Table 148. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz).

This is just an example from Clocking use case examples (RM, Section 24.7.2).
However, any clock frequency selected must adhere to the same clock divider ratios shown in Clocking use case examples.

Otherwise, we can't guarantee the specified functionality of the MCU.

Regards,

Daniel

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

jacopo_costella — Wed, 11 Oct 2023 11:28:04 GMT

Hello Daniel,

How did you check the incorrect core clock value? From the tool it is set to 120 MHz.

Regards,

Jacopo

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

danielmartynek — Wed, 11 Oct 2023 12:17:04 GMT

All the clocks must be set according to the table (including the PLL clock), or at least the ratios between the clocks must be maintained.

Regards,

Daniel

Re: Problem with Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat os S32K312

jacopo_costella — Wed, 11 Oct 2023 16:02:28 GMT

Hello Daniel,

problem fixed. Thank you very much,

Jacopo