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    <title>topic Re: Regarding DDR_DDRCDR_1,DDR_DDRCDR_2 and IFC_CSOR1_EXT registers  in QorIQ</title>
    <link>https://community.nxp.com/t5/QorIQ/Regarding-DDR-DDRCDR-1-DDR-DDRCDR-2-and-IFC-CSOR1-EXT-registers/m-p/843950#M7327</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;The manual is mistaken, all the mentioned registers has reset value 0x0. We will update T1024RM in the next release.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;Bulat&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 13 Sep 2018 06:27:41 GMT</pubDate>
    <dc:creator>Bulat</dc:creator>
    <dc:date>2018-09-13T06:27:41Z</dc:date>
    <item>
      <title>Regarding DDR_DDRCDR_1,DDR_DDRCDR_2 and IFC_CSOR1_EXT registers</title>
      <link>https://community.nxp.com/t5/QorIQ/Regarding-DDR-DDRCDR-1-DDR-DDRCDR-2-and-IFC-CSOR1-EXT-registers/m-p/843949#M7326</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial',sans-serif; color: black;"&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial',sans-serif; color: black;"&gt;The reset values for DDR_DDRCDR_1 is 0x00008080, DDR_DDRCDR_2 is 0x08000000 and IFC_CSOR1_EXT is 0x00100000 as per T1024 Reference manual. However when we read the value at reset the values always shows 0. For Eg: when we try to read the value&amp;nbsp;for IFC_CSOR1_EXT from offset address &lt;SPAN&gt;0x124140 &amp;nbsp;we are getting 0. Could you please let us know what are the possible reasons for reading the reset values for above register as 0?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="font-size: 10.0pt; font-family: 'Arial',sans-serif; color: black;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Aug 2018 04:47:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/QorIQ/Regarding-DDR-DDRCDR-1-DDR-DDRCDR-2-and-IFC-CSOR1-EXT-registers/m-p/843949#M7326</guid>
      <dc:creator>BharathiG</dc:creator>
      <dc:date>2018-08-30T04:47:15Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding DDR_DDRCDR_1,DDR_DDRCDR_2 and IFC_CSOR1_EXT registers</title>
      <link>https://community.nxp.com/t5/QorIQ/Regarding-DDR-DDRCDR-1-DDR-DDRCDR-2-and-IFC-CSOR1-EXT-registers/m-p/843950#M7327</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;The manual is mistaken, all the mentioned registers has reset value 0x0. We will update T1024RM in the next release.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 13px;"&gt;Bulat&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Sep 2018 06:27:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/QorIQ/Regarding-DDR-DDRCDR-1-DDR-DDRCDR-2-and-IFC-CSOR1-EXT-registers/m-p/843950#M7327</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2018-09-13T06:27:41Z</dc:date>
    </item>
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