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    <title>topic Re: DDR Validation Tool in QorIQ</title>
    <link>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617011#M4273</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;DDR controller from LS1012 board doesn't provide wrlv clock adjust and there are no registers for that. We don't have &amp;nbsp;in this moment an algorithm for DDR tuning for this SoC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Adrian&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 03 Mar 2017 08:24:27 GMT</pubDate>
    <dc:creator>addiyi</dc:creator>
    <dc:date>2017-03-03T08:24:27Z</dc:date>
    <item>
      <title>DDR Validation Tool</title>
      <link>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617010#M4272</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When I run the DDR validation tool, I don't see any scenarios for the 'Validation Stage'. I want to use these scenarios to properly configure the DDR3L chip I am using. I am using&amp;nbsp;CodeWarrior for ARMv8 targeted at the LS1012A&amp;nbsp;processor.&amp;nbsp;Is there anything I need to do to get these scenarios to appear?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="ddrvalidation.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/14908iD47CEA41BE91C66E/image-size/large?v=v2&amp;amp;px=999" role="button" title="ddrvalidation.PNG" alt="ddrvalidation.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Thanks for your help.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Mar 2017 19:54:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617010#M4272</guid>
      <dc:creator>justinjonas</dc:creator>
      <dc:date>2017-03-02T19:54:34Z</dc:date>
    </item>
    <item>
      <title>Re: DDR Validation Tool</title>
      <link>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617011#M4273</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;DDR controller from LS1012 board doesn't provide wrlv clock adjust and there are no registers for that. We don't have &amp;nbsp;in this moment an algorithm for DDR tuning for this SoC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Adrian&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Mar 2017 08:24:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617011#M4273</guid>
      <dc:creator>addiyi</dc:creator>
      <dc:date>2017-03-03T08:24:27Z</dc:date>
    </item>
    <item>
      <title>Re: DDR Validation Tool</title>
      <link>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617012#M4274</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you have any suggestions as to debug or tune a DDR chip with the LS1012?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Mar 2017 15:57:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617012#M4274</guid>
      <dc:creator>justinjonas</dc:creator>
      <dc:date>2017-03-03T15:57:03Z</dc:date>
    </item>
    <item>
      <title>Re: DDR Validation Tool</title>
      <link>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617013#M4275</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The DDR controller for LS1012 is very simple, so a working DDR configuration is enough for having a good configuration. Controller doesn't provide a way for fine tuning, it will just work or not.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Adrian&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Mar 2017 08:34:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/QorIQ/DDR-Validation-Tool/m-p/617013#M4275</guid>
      <dc:creator>addiyi</dc:creator>
      <dc:date>2017-03-14T08:34:19Z</dc:date>
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