topic Re: Controversial information about HDLC in different documents from NXP in QorIQ

Controversial information about HDLC in different documents from NXP

nxp_serge81 — Fri, 03 Feb 2017 08:22:33 GMT

Hi!

I'm trying to understand what HDLC modes are supported in different processors and I'm really confused.

For example, in QuiccEngine reference manual 7/2015 it's mentioned that for P1021/P1025/P1016/P1012 HDLC "Supported, but the ratio between the HDLC interface serial clock frequency and the QUICC Engine clock
frequency should be at least 1:14" (Chapter 14,p.1). In P1025 reference manual (rev1. 01/2013) it's said: "The ratio between the HDLC interface serial clock frequency and the QUICC Engine clock frequency should be at least 1:3" (p.1630).

Another example: in QuiccEngine ref manual 11/2015 there is an information that LS1021A,LS1020A support HDLC, in 7/2015 QE ref manual LS1021A, LS1020A are not listed in Table 14-1 at all, and from LS1021A datasheet (11/2016) I know that LS1021A supports HDLC, but lite version (synchronous HDLC isn't supported).

I got an answer for my question "Full-featured HDLC-ports on ref boards with communication processor", but MPC830x kit that supports synchronous full-duplex HDLC-interface is obsolete and MPC8309 is obsolete too. NXP suggests to migrate to QorIQ processors, so it doesn't make sense to use MPC8309 for a new design.

In TWR P1025 board there are 2 HDLC ports, but from Table 5-2 "I/O Connectors and Pin Usage Table" it's clear that there are no HDLC clock signals on the connectors, only RxD,TxD, CTS,RTS,CD! However, from P1025 ref manual (1/2013, p.71) we know that not only async HDLC is supported, but full-duplex with data rates up to 50Mbps. It's so frustrating... Is it possible to assign some GPIOs from QE SerialExpansion group of the TWR-P1025 board's connector as in and out clocks for sync HDLC?

What is BISYNC HDLC and how it works? Is it described in any document?

Sorry, but I just can't understand an overall concept of QE and sync HDLC (where to get/how to form Rx/Tx clocks, do I have to assign HDLC Rx/Tx clocks to GPIOs or there are dedicated clock pins, is it possible to use CTS/RTS from async HDLC/UART to flow control while sync HDLC is used, how to configure QE in P1025 to use sync HDLC). Hope to get some explanation from you.

Re: Controversial information about HDLC in different documents from NXP

Pavel — Tue, 07 Feb 2017 04:50:30 GMT

First of all look at NXP product longevity page:

http://www.nxp.com/about/about-nxp/technology-leadership/product-longevity/product-longevity-nxp-formerly-freescale-products:FSL-PRODUCT-LONGEVITY

This page shows that the MPC8309 product launched was 2011 and the MPC8309 is 10-years product.

The TWR-P1025 PB1 can be used as CLK5 or CLK10 for the HFLC. Find the J9A B23 on the TWR-P1025 schematic.

The LS1021a supports UCC1/UCC3. These UCC can be used for HDLC. See the Table 2-2 of the QE Reference Manual Rev 8:

https://www.nxp.com/webapp/Download?colCode=QEIWRM&Parent_nodeId=1281540457516714915076&Parent_pageType=product

See also the Section 30.3.5 of the LS1021A Reference Manual Rev 1:

https://www.nxp.com/webapp/Download?colCode=LS1021ARM&Parent_nodeId=1378142598972722203474&Parent_pageType=product

The ratio limitation for P1021/P1012/P1025/P1016 is actually a document error and it should be 1:3.The DOC team is in the process to update the document.

Note: Maximum HDLC clock is approximately 50Mbps for all QE devices.

Have a great day,
Pavel Chubakov

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Re: Controversial information about HDLC in different documents from NXP

nxp_serge81 — Wed, 08 Feb 2017 09:04:41 GMT

Pavel, is it possible to apply any external clk for ucc1/ucc3 on TWR-LS1021A to use sync HDLC on that board?

Re: Controversial information about HDLC in different documents from NXP

Pavel — Thu, 09 Feb 2017 04:46:12 GMT

The LS1021a QE contains UCC1 and UCC3. These UCC1 and UCC3 can use CLK9, CLK10, CLK11, CLK12, CLK15 and CLK16 as input clock signals.

The LS1021a pins are the following:

CLK9 - GPIO4_19

CLK10 - GPIO4_20

CLK11 - GPIO4_21

CLK12 - GPIO4_22

These pins are connected to HDMI transmitter (SiI9022A) on the TWR-LS1021A board.

It is means that external clock can be used for UCC1 or UCC3 on the TWr-LS1021a board.

If you want to use these pins as CLKx, resistors R98 or R100 or R101 or R375 should be removed and GPIO4_19 or GPIO4_20 or GPIO4_21 or GPIO4_22 is connected to your HDLC.

Have a great day,
Pavel Chubakov

Re: Controversial information about HDLC in different documents from NXP

nxp_serge81 — Thu, 09 Feb 2017 06:30:25 GMT

Thank you very much for your answers, Pavel.