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    <title>topic Re: Booting P1010 from SPI in Qonverge</title>
    <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685999#M338</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Rev.2 work perfect in debug mode (RAM) . Problem only with ROM mode... Can SEC engine to affect at code execution???&amp;nbsp;&lt;/P&gt;&lt;P&gt;P.S. we work in&amp;nbsp;&lt;SPAN style="color: #333333; background-color: #ffffff;"&gt;non-trusted system mode&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 07 Jul 2017 12:38:11 GMT</pubDate>
    <dc:creator>tsybezoff</dc:creator>
    <dc:date>2017-07-07T12:38:11Z</dc:date>
    <item>
      <title>Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685994#M333</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;STRONG style="background-color: #ffffff; color: #333333; font-size: 15px;"&gt;Hi to all!&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 15px;"&gt;We used the P1010 (part number&lt;STRONG&gt; P1010NSN5HHA&lt;/STRONG&gt;) with DDR 667MHz (MT41K256M16 - 4Gb) configuration , SPI boot and a non-trusted system mode. Now&amp;nbsp;we use&amp;nbsp;P1010 chip (part number &lt;STRONG&gt;P1010NXE5KHB&lt;/STRONG&gt;), and our embedded system (baremetal) is not working. After power-on reset we have&amp;nbsp;loading from SPI flash in ROM mode, but&amp;nbsp;CPU does not start (no&amp;nbsp;code execution). When we use the debugger CodeWarrior TAP (RAM mode), code executes&amp;nbsp;normally. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 15px;"&gt;What is the difference between chips by part number &lt;STRONG&gt;P1010NSN5HHA&lt;/STRONG&gt; and &lt;STRONG&gt;P1010NXE5KHB&lt;/STRONG&gt;? &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #333333; background-color: #ffffff; font-size: 15px;"&gt;How it affects system boot?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Jul 2017 08:21:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685994#M333</guid>
      <dc:creator>tsybezoff</dc:creator>
      <dc:date>2017-07-06T08:21:31Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685995#M334</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Partnumber decoding table from P1010 Hardware Specifications:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/25022iE2A76A79791615D1/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;So, differences are: Ext temp range instead of Std, Encryption block present, higher maximum core frequency and another silicon revision. The difference between silicon revisions is in several silicon bugs fixed, please see device errata for details.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The software may fail to boot because of several reasons, for example because of different SVR/PVR value.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Alexander&lt;BR /&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Jul 2017 13:19:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685995#M334</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2017-07-06T13:19:31Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685996#M335</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, Alex!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please, give us a link to&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;device errata for details!!!&lt;BR /&gt;You don't understand our question))) We want to know about differences in spi boot process (boot settings etc.) between&amp;nbsp;&lt;STRONG style="color: #333333; border: 0px; font-weight: bold;"&gt;P1010NSN5HHA&lt;/STRONG&gt;&lt;SPAN style="color: #333333;"&gt; and &lt;/SPAN&gt;&lt;STRONG style="color: #333333; border: 0px; font-weight: bold;"&gt;P1010NXE5KHB.&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 05:16:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685996#M335</guid>
      <dc:creator>tsybezoff</dc:creator>
      <dc:date>2017-07-07T05:16:52Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685997#M336</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have no problem with P1010 rev.1. Code is not executing at P1010 rev.2, however our embedded scheme is not change.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 05:24:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685997#M336</guid>
      <dc:creator>tsybezoff</dc:creator>
      <dc:date>2017-07-07T05:24:54Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685998#M337</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;P1010 device errata is currently "Preliminary, Confidential" and not available on our public site. Please contact your distributor to sign NDA and get this document.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There are no known bugs which may prevent rev.2 device from booting from SPI, if rev.1 works perfect. Please run your boot code under debugger control and determine, what exactly fails.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 11:17:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685998#M337</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2017-07-07T11:17:08Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685999#M338</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Rev.2 work perfect in debug mode (RAM) . Problem only with ROM mode... Can SEC engine to affect at code execution???&amp;nbsp;&lt;/P&gt;&lt;P&gt;P.S. we work in&amp;nbsp;&lt;SPAN style="color: #333333; background-color: #ffffff;"&gt;non-trusted system mode&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Jul 2017 12:38:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/685999#M338</guid>
      <dc:creator>tsybezoff</dc:creator>
      <dc:date>2017-07-07T12:38:11Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/686000#M339</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can we work in non-secure mode with &lt;STRONG style="color: #333333; border: 0px; font-weight: bold;"&gt;P1010NXE5KHB?&lt;BR /&gt;&lt;/STRONG&gt;We change chip&amp;nbsp;&lt;STRONG style="color: #333333; border: 0px; font-weight: bold;"&gt;P1010NSN5HHA&amp;nbsp;&lt;/STRONG&gt;for&amp;nbsp;&lt;STRONG style="color: #333333; border: 0px; font-weight: bold;"&gt;P1010NXE5KHB&lt;/STRONG&gt;. As result our system doesn't work (in debug it works perfect). SPI booting is complete after reset on-chip, but CPU is not running.&lt;BR /&gt;What's the problem, guys???&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Jul 2017 10:36:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/686000#M339</guid>
      <dc:creator>tsybezoff</dc:creator>
      <dc:date>2017-07-11T10:36:48Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/686001#M340</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, the &lt;SPAN style="color: #333333; background-color: #ffffff; border: 0px; font-weight: bold;"&gt;&lt;STRONG&gt;P1010NXE5KHB &lt;/STRONG&gt;&lt;/SPAN&gt;can work in non-secure mode. The fact that security block is available - should not prevent the device from booting, if boot code does not use this block. The fact that RAM mode works, but only ROM image does not work - does not mean that the problem is related to security block.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Please run your ROM code under debugger control and determine, what exactly fails.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Jul 2017 16:02:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/686001#M340</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2017-07-11T16:02:17Z</dc:date>
    </item>
    <item>
      <title>Re: Booting P1010 from SPI</title>
      <link>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/686002#M341</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We fixed the problem. In ROM init source we commented a row of&amp;nbsp;source code at&amp;nbsp;Tlb1Entries:&amp;nbsp;0x10030000, 0x80000100, 0xFF70000A, 0xFF700015&lt;SPAN class=""&gt; &lt;/SPAN&gt; //# define 4KB&lt;SPAN class=""&gt; &lt;/SPAN&gt; &amp;nbsp; TLB1 entry 3: 0xFF700000 - 0xFF7FFFFF; for default CCSR Space (old)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please, explain this part of TLB settings. We didn't find any info about that.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jul 2017 06:26:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Qonverge/Booting-P1010-from-SPI/m-p/686002#M341</guid>
      <dc:creator>tsybezoff</dc:creator>
      <dc:date>2017-07-17T06:26:44Z</dc:date>
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