T1024 reset Issue

sri-cdot — Wed, 23 Nov 2016 10:41:18 GMT

We are working on T1024 based custom board. We didn't use FPGA. We are trying to make reset operation to work in uboot.

For this, we are trying to access core registers Debug Control Register (DBCR0) for reset and

External Debug Resource Allocation Register 0 (EDBRAC0) for allocating resources.

In EDBRAC0:

33 bit - Internal Debug Mode control - set to '1'

34 bit - Reset field control allocation - set to '1'

In DBCR0:

33 bit - Internal debug mode - set to '1'

34–35 bits - Reset Control - set to '11'

These changes we made in "do_reset()" funtion in arch/powerpc/cpu/mpc85xx/cpu.c and compiled

But in the Uboot we are getting below error.

----------------------------------------------------------------------------------------------------------------------------------

=> reset
init_board_reset
NIP: 7FEF76E4 XER: 00000000 LR: 7FEF76E4 REGS: 7f4edc30 TRAP: 0700 DAR: 00000000
MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 7FEF76E4 7F4EDD20 7F4EDEF8 00000013 00000020 7F4EDCE4 7F4F1A50 00000000
GPR08: 00000000 00000020 00000020 7F4EDD20 7FF141E4 00000000 7FFB0328 7F4F1A50
GPR16: 7FF54A24 7FF54388 7F4F1A50 7F4F1A40 7F4F1A70 00000000 00000000 00000000
GPR24: 00000000 7FFB01EC 00000001 7F4F1A50 00000000 00000000 7FF67190 7FF75A94
** Illegal Instruction **
Call backtrace:
7FEF76E4 7FEF7A50 7FF19EA0 7FEFC5F0 7FEFCDA0 7FEFCE44 7FF188F4
7FEFD690 7FF42C24 7FEFD9AC 7FEF1650
Program Check Exception
### ERROR ### Please RESET the board ###

----------------------------------------------------------------------------------------------------------------------------------

How to fix this issue or is there any other way to make reset to work ?

Please help on this.

Regards,

sridhar

Re: T1024 reset Issue

ufedor — Wed, 23 Nov 2016 14:23:13 GMT

The only supported method of generating processor reset is setting DCFG_CCSR_RSTCR[RESET_REQ]=1.

Further RST_REQ_B can be used to trigger PORESET_B assertion.

Re: T1024 reset Issue

sri-cdot — Thu, 24 Nov 2016 04:40:11 GMT

Thanks for your response.

In our board, reset_req_n signal is a floating output, we didn't connect it to PORESET_n, so we are trying for alternate method to generate reset.

Is it possible to implement the reset, with watch dog timer ?

if it is, please guide us on implementing the watchdog timer reset.

Regards,

Sridhar

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