QonvergeのトピックRe: MPC823ERDB 256MB DDR Support.

MPC823ERDB 256MB DDR Support.

vidyasagartata — Fri, 03 Jun 2016 05:02:13 GMT

Dear All,

We have developed custom MPC8323ERDB board.

We have 256MBytes DDR-2 SDRAM (MT4764M16 - 8Megx16x8banks) on board, we are able to access (read/write) 128Mbytes in u-boot.

Need to configure 256MBytes in u-boot.

Please let me know what configuration is needed access 256Mbytes DDR-2 SDRAM in u-boot.

Thanks,

Vidya

Re: MPC823ERDB 256MB DDR Support.

Bulat — Fri, 03 Jun 2016 06:39:03 GMT

DDR SDRAM size should be properly set in three places:

1) DDR controller itself;

2) SDRAM local access window;

3) IBAT/DBAT MMU registers.

Try to check if all these settings are correct.

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Fri, 03 Jun 2016 08:33:54 GMT

Hi Bulat,

I changed following parameters according to the 8323RM and DDR-2 data sheet,

DDR_CS0_CONFIG 256 // old = 64

DDR_CS0_BNDS 0x0000000F // old = 0x00000003

128MBytes DDR SDRAM works fine at following configuration (include/configs/MPC8323ERDB.h)

DDR_CS0_CONFIG 128	// old = 64
DDR_CS0_BNDS 0x00000007	// old = 0x00000003

MMU setup is always (Both cases)

CONFIG_HIGH_BATS 1

Please let me know any other value need to modified to access (read/write) 256MBytes DDR SDRAM.

Thanks,

Vidya

Re: MPC823ERDB 256MB DDR Support.

Bulat — Fri, 03 Jun 2016 13:01:19 GMT

Following line is a bit doubtful:

DDR_CS0_CONFIG 256 // old = 64

Can you check it once again?

--------------------------------------------------------------------

1) I believe you were going to set :

#define CONFIG_SYS_DDR_SIZE 256 /* MB */

2) DDR_CS0_CONFIG should be 0x80014102 in your case.

3) Check that CONFIG_SYS_IBAT0U is set to BATU_BL_256M size.

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Sat, 04 Jun 2016 05:53:45 GMT

Dear Bulat,

You are correct

#define CONFIG_SYS_DDR_SYS 256 // MB

#define CONFIG_SYS_CS0_CONFIG 0x80844102 // old = 80840102

#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP )

Also changed the timing parameters for accessing (read/write) 256 MBytes

#define CONFIG_SYS_DDR_TIMING_1 0x26256222 //old = 0x3935d342

#define CONFIG_SYS_DDR_TIMING_2 0x0f9028c7 //old =0x0f9030c7

256MBytes detects in u-boot as well as in kernel also cat /proc/meminfo shows MemTotal: 255012 KB

but Ethernet is not working in both u-boot and kenrnel and also getting restarted if i do ping.

Please let me know any more parameter need to change for accessing (read/write) 256MBytes DDR SDRAM memory.

Thanks,

Sagar

Re: MPC823ERDB 256MB DDR Support.

Bulat — Mon, 06 Jun 2016 06:31:39 GMT

Can you clarify if something has changed after your original question? You wrote "we are able to access (read/write) 128Mbytes in u-boot", is it still so? You did not mention the word "ethernet" in the first question.

What is the MCK frequency on the DDR bus?

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Mon, 06 Jun 2016 10:47:21 GMT

Dear Bulat,

There is no problem in the 128MBytes read and write and in this case both Ethernet ports work.

But when enabled the 256MBytes DDR SRAM,in this case both Ethernet port do not work.

Whenever ping, gets hang.

MCK ferquency on the DDR bus = 133.33 MHz.

Thanks,

Sagar

Re: MPC823ERDB 256MB DDR Support.

Bulat — Tue, 07 Jun 2016 07:03:27 GMT

Following line is not correct for 133MHz, DDR2 fucntionality will be corrupted:

#define CONFIG_SYS_DDR_TIMING_1 0x26256222 //old = 0x3935d342

It needs to be like following:

#define CONFIG_SYS_DDR_TIMING_1 0x2625A222

Also we recommend that WL+AL should be a minimum of 3 cycles for the ODT to be asserted correctly. In your case AL=0, so this recommendation is not met.

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Tue, 07 Jun 2016 10:30:21 GMT

Dear Bulat,

I have changed but facing same problem.

I have attached the MPC8323ERDB.h config file.

Please help me to solve the issue.

Thanks,

Sagar

Re: MPC823ERDB 256MB DDR Support.

Bulat — Wed, 08 Jun 2016 07:52:49 GMT

As I can see you sent old header file, values of DDR controller do not correspond to mentioned above. For example:

#define CONFIG_SYS_DDR_TIMING_2 0x0f9030c7

You mentioned:

#define CONFIG_SYS_DDR_TIMING_2 0x0f9028c7 //old =0x0f9030c7

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Wed, 08 Jun 2016 09:10:30 GMT

Dear Bulat,

If i changed the value of

#define CONFIG_SYS_DDR_TIMINING_2 0x0f9030c7

and cross ported compiled u-boot but is same, Ethernet ports are not working.

Thanks,

Sagar

Re: MPC823ERDB 256MB DDR Support.

Bulat — Fri, 10 Jun 2016 11:12:45 GMT

Again, header file seems to be old. Another example from the file:

#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102

This value corresponds to 128MB memory size.

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Mon, 13 Jun 2016 11:57:18 GMT

Dear Bulat,

I have chenged

#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102

#define CONFIG_SYS_DDR_TIMINING_2

0x0f9030c7

and tested DDR2 SDRM but result is same.

Please suggest me what is the issue.

Thanks,

Sagar

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Tue, 14 Jun 2016 11:34:49 GMT

I have changed the macros

#define CONFIG_SYS_CS0_CONFIG 0x80844102

#define CONFIG_SYS__DDR_TIMING_2 0xf9028c7

But still ping does not happen.

Thanks,

Vidya

Re: MPC823ERDB 256MB DDR Support.

Bulat — Wed, 15 Jun 2016 12:41:04 GMT

Can you attach actual header file (for 256MB) and actual schematics of the DDR interface?

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Fri, 17 Jun 2016 05:52:49 GMT

Dear Bulat,

Please find the header file for DDR below:

* DDR Setup

#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */

#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE

#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE

#define CONFIG_SYS_DDRCDR 0x62000002

#undef CONFIG_SPD_EEPROM

#if defined(CONFIG_SPD_EEPROM)

/* Determine DDR configuration from I2C interface

#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */

#else

/* Manually set up DDR parameters

/*#define CONFIG_SYS_DDR_SIZE 64 */ /* MB */

#define CONFIG_SYS_DDR_SIZE 256 /* MB */

/* #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \

| CSCONFIG_ROW_BIT_13 \

| CSCONFIG_COL_BIT_9) */

/* 0x80010101 */

//#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102

#define CONFIG_SYS_DDR_CS0_CONFIG 0x80844102

#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \

| (0 << TIMING_CFG0_WRT_SHIFT) \

| (0 << TIMING_CFG0_RRT_SHIFT) \

| (0 << TIMING_CFG0_WWT_SHIFT) \

| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \

| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \

| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \

| (2 << TIMING_CFG0_MRS_CYC_SHIFT))

/* 0x00220802 */

/*#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \

| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \

| (2 << TIMING_CFG1_ACTTORW_SHIFT) \

| (5 << TIMING_CFG1_CASLAT_SHIFT) \

| (3 << TIMING_CFG1_REFREC_SHIFT) \

| (2 << TIMING_CFG1_WRREC_SHIFT) \

| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \

| (2 << TIMING_CFG1_WRTORD_SHIFT)) */

/* 0x26253222 */

//#define CONFIG_SYS_DDR_TIMING_1 0x3935d342

#define CONFIG_SYS_DDR_TIMING_1 0x26256222

#define CONFIG_SYS_DDR_TIMING_2 0x0f9028c7

#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \

| (31 << TIMING_CFG2_CPO_SHIFT) \

| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \

| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \

| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \

| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \

| (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) */

/* 0x1f9048c7 */

#define CONFIG_SYS_DDR_TIMING_3 0x00000000

#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05

/* 0x02000000 */

/*#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ */

#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \

| (0x0232 << SDRAM_MODE_SD_SHIFT))

/* 0x44480232 */

#define CONFIG_SYS_DDR_MODE2 0x8000c000

/* #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ */

#define CONFIG_SYS_DDR_INTERVAL ((0x00c8 << SDRAM_INTERVAL_REFINT_SHIFT) \

| (0x0064 << SDRAM_INTERVAL_BSTOPRE_SHIFT))

/* 0x03200064 */

/*#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 */

//#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007

#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F

#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000

/*#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \

| SDRAM_CFG_SDRAM_TYPE_DDR2 \

| SDRAM_CFG_32_BE) */

/* 0x43080000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000

#endif

* Memory test

#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */

#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */

//#define CONFIG_SYS_MEMTEST_END 0x03f00000

#define CONFIG_SYS_MEMTEST_END 0x07f00000

* The reserved memory

#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)

#define CONFIG_SYS_RAMBOOT

#else

#undef CONFIG_SYS_RAMBOOT

#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */

//#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */

#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 384 kB for Mon */

#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */

* Initial RAM Base Address Setup

#define CONFIG_SYS_INIT_RAM_LOCK 1

#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */

#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET \

(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

* Local Bus Configuration & Clock Setup

#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP

#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2

#define CONFIG_SYS_LBC_LBCR 0x00000000

* FLASH on the Local Bus

#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */

#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */

//#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */

#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* FLASH base address */

//#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */

#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 16M */

//#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */

/* Window base at flash base */

#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE

//#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)

#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000019

#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \

| BR_PS_16 /* 16 bit port */ \

| BR_V) /* valid */

#define CONFIG_SYS_OR0_PRELIM 0xFC000FF7

/*#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \

| OR_GPCM_XAM \

| OR_GPCM_CSNT \

| OR_GPCM_ACS_DIV2 \

| OR_GPCM_XACS \

| OR_GPCM_SCY_15 \

| OR_GPCM_TRLX_SET \

| OR_GPCM_EHTR_SET \

| OR_GPCM_EAD) */

/* 0xFE006FF7 */

#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */

//#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */

#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/* Second Flash */

#define CONFIG_FLASH1_BASE 0x88000000

#define CONFIG_LBLAWBAR1_PRELIM CONFIG_FLASH1_BASE

#define CONFIG_LBLAWAR1_PRELIM 0x80000019 /*LBLAWAR2 - enable, size = 64MB */

#define CONFIG_SYS_BR1_PRELIM (CONFIG_FLASH1_BASE | /* Flash Base address */ \

(2 << BR_PS_SHIFT) | /* 16 bit port size */ \

BR_V) /* valid */

#define CONFIG_SYS_OR1_PRELIM 0xFC000FF7 /* Mask for 64MB Flash size */

* Memory map for DS0 Cross Connect

#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xFC000000

#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /*LBLAWAR2 - enable, size = 128KB*/

//#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000011 /*LBLAWAR2 - enable, size = 256KB*/

#define CONFIG_SYS_BR2_PRELIM 0xFC001001 /* BR2 base address at 0xFA008000, port size 16 bit, */

#define CONFIG_SYS_OR2_PRELIM 0xFFFE0FF7 /* OR2 128KB size */

//#define CONFIG_SYS_OR2_PRELIM 0xFFFC0FF7 /* OR2 256KB size */

Please find the DDR section:

Re: MPC823ERDB 256MB DDR Support.

Bulat — Fri, 17 Jun 2016 07:39:54 GMT

1. Please take a look at my post dated 07.06.2016 and make required changes.

2. Your schematics is not well visible due to low resolution.

After changes are made, please take following memory dumps in uboot:

md e0000000 40

md e0002000 80

Regards,

Bulat

Re: MPC823ERDB 256MB DDR Support.

vidyasagartata — Sun, 19 Jun 2016 05:28:04 GMT

Dear Bulat,

Please find log below:

U-Boot 2014.07-00038-g659b6a2-dirty (Jun 19 2016 - 10:01:26)MPC83XX

Reset Status: Software Hard, External/Internal Soft, External/Internal Hard

CPU: e300c2, MPC8321E, Rev: 1.1 at 333.333 MHz, CSB: 133.333 MHz

Board: Freescale MPC8323ERDB

I2C: ready

DRAM: 256 MiB (DDR2, 32-bit, ECC off, 266.667 MHz)

Flash: 256 MiB

*** Warning - bad CRC, using default environment

In: serial

Out: serial

Err: serial

Net: UEC1, UEC3

Hit any key to stop autoboot: 0

=> md 0xe0000000 0x40

e0000000: e0000000 00000000 00000000 00000000 ................

e0000010: 00000000 00000000 00000000 00000000 ................

e0000020: 80000000 80000019 00000000 00000000 ................

e0000030: fc000000 80000010 f8000000 80000019 ................

e0000040: 00000000 00000000 00000000 00000000 ................

e0000050: 00000000 00000000 00000000 00000000 ................

e0000060: 00000000 00000016 00000000 00000000 ................

e0000070: 00000000 00000000 00000000 00000000 ................

e0000080: 00000000 00000000 00000000 00000000 ................

e0000090: 00000000 00000000 00000000 00000000 ................

e00000a0: 00000000 8000001b 00000000 00000000 ................

e00000b0: 00000000 00000000 00000000 00000000 ................

e00000c0: 00000000 00000000 00000000 00000000 ................

e00000d0: 00000000 00000000 00000000 00000000 ................

e00000e0: 00000000 00000000 00000000 00000000 ................

' - try 'help'