topic Re: powerpc interrupt processing/JMP instruction in PowerQUICC Processors

powerpc interrupt processing/JMP instruction

shantanunakhate — Wed, 24 Jul 2013 13:09:32 GMT

Hello,

When Interrupt occurs during powerpc execution , what does the powerpc do? will it complete the current instruction execution and then jump to ISR or will it suspend the instruction execution , and execute the same instruction after executing ISR?

consider the following instruction under execution JUMP xxxxx.

so when an interrupt occurs during this instruction execution , does powerpc complete jmp instruction and then go to ISR or it will suspend JMP instruction execute ISR and then

execute JMP instruction again freshly ?

does the case same with move instruction ?

Regards

Re: powerpc interrupt processing/JMP instruction

marius_grigoras — Wed, 24 Jul 2013 14:10:32 GMT

Hi,

Please let me know the core and also the interrupt type (program, TLB, system call etc).

Thank you,

Marius

Re: powerpc interrupt processing/JMP instruction

lunminliang — Thu, 25 Jul 2013 03:26:21 GMT

This query also relates to MPC8349?

Re: powerpc interrupt processing/JMP instruction

shantanunakhate — Thu, 25 Jul 2013 05:58:36 GMT

MPC8343 and the interrupt would be external interrupt ( GPIO configured as external IRQ)

Re: powerpc interrupt processing/JMP instruction

shantanunakhate — Thu, 25 Jul 2013 06:01:54 GMT

Its MPC8343

Re: powerpc interrupt processing/JMP instruction

lunminliang — Fri, 26 Jul 2013 01:06:55 GMT

See below technical support comment:

IRQ is a Integrated Programmable Interrupt Controller (IPIC) input. The interrupt sources controlled by the IPIC unit cause exceptions in the processor core (e300 in the MPC834x). The IPIC can assign int, cint and smi signals of the core. Internal interrupt (int) signal is the main interrupt output from the IPIC to the core.

The external interrupt (int), system management interrupt (smi), decrementer interrupt, and critical interrupt (cint) are maskable asynchronous interrupts. When these interrupts occur, their handling is postponed until the next instruction completes execution and until any interrupts associated with that instruction complete execution. If there are no instructions in the execution units, the interrupt is taken immediately upon determination of the correct restart address (for loading SRR0).

More details in Chapter “Interrupts and Exceptions” of e300 Power Architecture Core Family Reference Manua http://cache.freescale.com/files/32bit/doc/ref_manual/e300coreRM.pdf

Re: powerpc interrupt processing/JMP instruction

scottwood — Mon, 12 Aug 2013 19:11:24 GMT

The interrupted execution will either be completed or aborted. Given the pipelined nature of the CPU it doesn't really make sense to talk about being in the middle of a specific instruction when the interrupt comes in -- it's likely that the CPU was in the middle of executing several instructions. By the time the CPU starts executing at the exception vector, it will have sorted things out such that the interrupted state is consistent and restartable.

One notable situation is when the CPU was executing a guarded load instruction. Since guarded accesses can't be retried (or else the device would see two accesses, which may have side effects), and a load instruction can't complete until data is returned, if an interrupt happens after a guarded load has gone out on the bus, the CPU will wait for the guarded load to complete before taking the interrupt.