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    <title>topic Re: MPC8308:DDR2 memory space overlapped in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8308-DDR2-memory-space-overlapped/m-p/277541#M522</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;At first sight your DDR initialization is not complete -- it's mandatory to set up and the rest DDR registers (for timings, SDRAM modes and so on). Please find attached 2 files (for 8308SOM and 8308_mITX boards) where you can find some full DDR inits. Please note that these files are for some ROM applications - you can ignore the rest init parts for eLBC modules and so on.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Marius&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 06 Jun 2013 08:15:22 GMT</pubDate>
    <dc:creator>marius_grigoras</dc:creator>
    <dc:date>2013-06-06T08:15:22Z</dc:date>
    <item>
      <title>MPC8308:DDR2 memory space overlapped</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8308-DDR2-memory-space-overlapped/m-p/277540#M521</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi:&lt;BR /&gt;I meet a problem about the memory access when I do some develop job on my own board based on mpc8308.&lt;BR /&gt;Below is the detail description.&lt;/P&gt;&lt;P&gt;Hardware Environment:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; CPU:MPC8308&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR2:MT47H64M16HR(2 chips,256MBytes in total)&lt;BR /&gt; Note:The schematic will shows you that the connection between CPU and DDR2_Memory Device.&lt;/P&gt;&lt;P&gt;DDR2 initialize sequence as follows(Configure the registers associate with the DDR2 Memory Controller):&lt;/P&gt;&lt;P&gt;# DDR2 local access window 0 attribute regster (DDRLAWAR0)&lt;/P&gt;&lt;P&gt; lis&amp;nbsp; r5, 0x8000&lt;BR /&gt; ori&amp;nbsp; r5, r5, 0x001b&lt;BR /&gt; lis&amp;nbsp; r4, &lt;A href="mailto:0xe00000a4@ha"&gt;0xe00000a4@ha&lt;/A&gt;&lt;BR /&gt; stw&amp;nbsp; r5, &lt;A href="mailto:0xe00000a4@l(r4"&gt;0xe00000a4@l(r4&lt;/A&gt;)&lt;/P&gt;&lt;P&gt;#Chip Select Bounds Registers (CS0_BNDS)&lt;BR /&gt; lis&amp;nbsp; r5, 0x0000&lt;BR /&gt; ori&amp;nbsp; r5, r5, 0x000f&lt;BR /&gt; lis&amp;nbsp; r4, &lt;A href="mailto:0xe0002000@ha"&gt;0xe0002000@ha&lt;/A&gt;&lt;BR /&gt; stw&amp;nbsp; r5, &lt;A href="mailto:0xe0002000@l(r4"&gt;0xe0002000@l(r4&lt;/A&gt;)&lt;/P&gt;&lt;P&gt;After congiguring the DDR2 Memory controller as above,I found a strange problem when I do some memory access operations,the lower 128MB space is overlapped with the upper 128MB space,such as:&lt;/P&gt;&lt;P&gt; int * p = (int *)0x01000000;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; *p = 0x12345678;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #ff0000;"&gt;&lt;STRONG&gt;after the operation above,I found the space 0x01000000 &amp;amp; 0x09000000 were filled with the same value(0x12345678).&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;(I guess becuz some steps of the configuration were wrong and it caused the MSB(bit27) of the address line of DDR2 doesn't work)&lt;/P&gt;&lt;P&gt;what causes this and why?please help me?&lt;/P&gt;&lt;P&gt;Thanks very much!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Jun 2013 07:13:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8308-DDR2-memory-space-overlapped/m-p/277540#M521</guid>
      <dc:creator>gengdongwan</dc:creator>
      <dc:date>2013-06-06T07:13:55Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8308:DDR2 memory space overlapped</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8308-DDR2-memory-space-overlapped/m-p/277541#M522</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;At first sight your DDR initialization is not complete -- it's mandatory to set up and the rest DDR registers (for timings, SDRAM modes and so on). Please find attached 2 files (for 8308SOM and 8308_mITX boards) where you can find some full DDR inits. Please note that these files are for some ROM applications - you can ignore the rest init parts for eLBC modules and so on.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Marius&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Jun 2013 08:15:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8308-DDR2-memory-space-overlapped/m-p/277541#M522</guid>
      <dc:creator>marius_grigoras</dc:creator>
      <dc:date>2013-06-06T08:15:22Z</dc:date>
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