topic Re: MPC555 abnormal into LIMP mode in PowerQUICC Processors

MPC555 abnormal into LIMP mode

andes — Tue, 13 May 2025 01:55:36 GMT

MPC555 abnormal into LIMP mode

We have a legacy design using MPC555LFMVR40.

The system input is 40MHz clock to the MPC555. In normal startup, the clock of the MPC555 is 40MHz. Sometimes we found the clock output from the MPC555 is 7MHz, which corresponds to a limp mode according to the manual. We checked the manual, and this mode is related to the status of several pins (MODCK1/2/3), and we also measured the status but found no abnormalities.

Could some help me to understand what would lead the chip enter LIMP mode?

I know this part is EOL but we bought stock per LTB that could support our commitment to end customer till 2035. We do need NXP support the investigate on the root cause. Please do the best to give some comments on any possible reason that will cause the chip run into LIMP mode. Thanks!

From Royal Philips.

Re: MPC555 abnormal into LIMP mode

lukaszadrapa — Wed, 14 May 2025 11:24:06 GMT

Hi @andes

This is deep history, please give me more time to gather some details.

Regards,

Lukas

Re: MPC555 abnormal into LIMP mode

lukaszadrapa — Thu, 15 May 2025 06:28:33 GMT

Hi @andes

The Limp mode is entered in case of loss of clock:

lukaszadrapa_0-1747290441831.png

If you take a look at the errata sheet for revision M, there's an explanation (CDR_AR_598) that some boards can be more sensitive to PLL issues. There's a list of recommendations which should help to avoid that and recommendation how to deal with such event:
https://www.nxp.com/docs/en/errata/MPC555MCE.pdf

lukaszadrapa_1-1747290490447.png

Regards,
Lukas

Re: MPC555 abnormal into LIMP mode

andes — Wed, 21 May 2025 07:17:41 GMT

Thank you Lukas! Passed this message to customer engineer for further study / troubleshooting. Will come back for further support if needed.