topic MCP7448 60x amount of bytes to tranfer in PowerQUICC Processors

MCP7448 60x amount of bytes to tranfer

addi — Tue, 23 Jan 2024 07:26:04 GMT

Im going to simulate MCU working under 60x bus.

But according to the documentation I can't get understanding in the following data transfer modes:

1) burst dara transfer, - up to 32 bytes or 32 bytes only?

2) single beat, - from 1 byte and up to 8 bytes?

3) double beat, - up to 16 bytes or 16 bytes only?

4) L2 cache reading/writing is only possible in burst mode?

Please help in understanding

yipingwang — Mon, 29 Jan 2024 09:22:24 GMT

addi — Wed, 28 Feb 2024 18:02:58 GMT

Thank you fro your replay!

I checked this document in relating of my question and unfortunally didn't find the answer still

Thus I asking to correct me in the following assignments of my understanding:

1) burst dara transfer is for L2 cache reading/writing

2) single beat is in range from 1 byte and up to 8 bytes

3) L2 cache reading/writing is only possible in burst mode

4) L2 cache reading/writing is possible in four or more bus cycles