https://community.nxp.com/t5/PowerQUICC-Processors/T1024-and-DDR4/m-p/1755102#M4495 <P>Please make sure that your design is following all the requirements in AN5097(&nbsp;Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces), after that review your RCW's values, all your power supplies around DDR(measured values) and check if SYSCLK frequency is correct.</P> Thu, 09 Nov 2023 17:28:24 GMT Oswalag 2023-11-09T17:28:24Z https://community.nxp.com/t5/PowerQUICC-Processors/T1024-and-DDR4/m-p/1750988#M4492 <P>T1024 and DDR4</P><P>Err. capture registers:<BR />0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080<BR />0xE44, 0x00000000 0xE48, 0x0000001D 0xE4C, 0x00000000 0xE50, 0x00000000<BR />0xE54, 0x00000000 0xE58, 0x00010000</P><P>Exception: (&lt;&lt;Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware!&gt;&gt;)</P><P>Exception: (&lt;&lt;ERR_DETECT register is not empty, test did not run.&gt;&gt;)</P><P>What could be the reason？Can you help me check the schematic design？</P> Thu, 02 Nov 2023 09:12:54 GMT https://community.nxp.com/t5/PowerQUICC-Processors/T1024-and-DDR4/m-p/1750988#M4492 wang152 2023-11-02T09:12:54Z https://community.nxp.com/t5/PowerQUICC-Processors/T1024-and-DDR4/m-p/1755102#M4495 <P>Please make sure that your design is following all the requirements in AN5097(&nbsp;Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces), after that review your RCW's values, all your power supplies around DDR(measured values) and check if SYSCLK frequency is correct.</P> Thu, 09 Nov 2023 17:28:24 GMT https://community.nxp.com/t5/PowerQUICC-Processors/T1024-and-DDR4/m-p/1755102#M4495 Oswalag 2023-11-09T17:28:24Z