topic Re: MPC8548E : PCB Layout Guidelines for Local Bus Interface signals in PowerQUICC Processors

MPC8548E : PCB Layout Guidelines for Local Bus Interface signals

sagar_bn — Tue, 26 Apr 2022 14:42:47 GMT

Please provide PCB Layout guidelines for Local Bus interface signals of MPC8548E.

Should we follow any length matching for LAD[0:31] signals ?

Please also let us know about all the local bus interface signals for which layout guide has to be followed.

Re: MPC8548E : PCB Layout Guidelines for Local Bus Interface signals

yipingwang — Thu, 28 Apr 2022 01:28:45 GMT

No general document is avialable. What is the device intended for interfacing?

Maybe some Freescale evaluation boards can be referred.

Re: MPC8548E : PCB Layout Guidelines for Local Bus Interface signals

sagar_bn — Thu, 28 Apr 2022 09:32:31 GMT

We are using Local Bus Interface of MPC8548E for interfacing with many devices like NOR Flash, NAND Flash, NVSRAM, and two FPGAs.

These signals are running throughout my VPX standard board because of multiple components at different locations.

Please share if any Evaluation board file available.

Re: MPC8548E : PCB Layout Guidelines for Local Bus Interface signals

yipingwang — Thu, 05 May 2022 02:19:18 GMT

Please find attached 8548CDS board design material. All people generated this files are gone. It is prepared by Mentor Graphics and it is not Cadence that board team are using. Simple put, no support for this file.

Alternatively, please refer to P4080DS material local bus design if the customer cannot make use of 8548 file.