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    <title>PowerQUICC Processors中的主题 Re: P1022: Console hangs after PCIE error dump</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1438684#M4121</link>
    <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411"&gt;@yipingwang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can we avoid the CPU to go into inconsistent state in case of PCI Express completion time-out.&lt;/P&gt;&lt;P&gt;As per our understanding The CPU has to report the PCIe error and continue its process.&lt;/P&gt;&lt;P&gt;We need the Host CPU in running state to further debug and find out the root cause of the problem at framer device.&lt;/P&gt;</description>
    <pubDate>Tue, 05 Apr 2022 06:30:59 GMT</pubDate>
    <dc:creator>hemwant</dc:creator>
    <dc:date>2022-04-05T06:30:59Z</dc:date>
    <item>
      <title>P1022: Console hangs after PCIE error dump</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1364368#M3939</link>
      <description>&lt;P&gt;We are having P1022 based customized board, the processor gets struck after throwing pci error dump and nothing is accessible via console or telnet session . The log of the dump is as follows-&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyGetLineFecCounters: TPN-PM:: ADDING index 11 intf_id 1&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyGetLineFecCounters: TPN-PM :: fec corr+9*uncorr[1][11] : 4&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyMapOtnIntfIdToSlice: PM: intf type 27 intf id 2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyMapOtnIntfIdToSlice: PM:otn line 1-7 9&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyGetLineOtnParams: TPN-PM :: **SAMPLE PM-BIP errors 1451, intf id :2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyGetLineOtnParams: TPN-PM :: **SAMPLE PM-BEI errors 0, intf id :2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: TPN-PM :: odu_pm_es[684] : 1&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: TPN-PM :: odu_pm_ses[684] : 0&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: TPN-PM :: odu_pm_bbe[684] : 1451&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: TPN-PM :: odu_pm_fees[684] : 0&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: TPN-PM :: odu_pm_feses[684] : 0&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: TPN-PM :: odu_pm_bbe[684] : 0&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.crit TPN[2206]: CalcOtnErrorParamsGeneric: odu_pm_bip_errors: 1451&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyGetLineOtnParams: TPN-PM :: **SAMPLE SM-BIP errors 1732, intf id :2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.info TPN[2206]: PmHyPhyGetLineOtnParams: TPN-PM :: **SAMPLE SM-BEI errors 1733, intf id :2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Oct 29 17:11:25 p1022ds local5.err TPN[2206]: PmHyPhyGetLineFecCounters: PM:no dev init / wrong intf id 2&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Card type value 1 4The AlarmStaus is 1 of bit 12The AlarmStaus is 1 of bit 14The AlarmStaus is 1 of bit 8The AlarmStaus is 1 of bit 10The AlarmStaus is 0 of bit 15The AlarmStaus is 1 of bit 11The AlarmStaus is 0 of bit 14The AlarmStaus is 1 of bit 7The AlarmStaus is 1 of bit 8The AlarmStaus is 0 of bit 9The PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: AER: Uncorrected (Non-Fatal) error received: id=0100&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: AER: Uncorrected (Non-Fatal) error received: id=0100&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: AER: Uncorrected (Non-Fatal) error received: id=0100&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: AER: Uncorrected (Non-Fatal) error received: id=0100&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x80800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: AER: Multiple Uncorrected (Non-Fatal) error received: id=0100&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: PCIe Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, id=0000(Requester ID)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: device [1957:0110] error status/mask=00004000/00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe error(s) detected&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_DR register: 0x00800000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_STAT register: 0x00000041&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R0 register: 0x00000800&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R1 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R2 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;PCIe ERR_CAP_R3 register: 0x00000000&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pcieport 0000:00:00.0: [14] Completion&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 01 Nov 2021 07:05:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1364368#M3939</guid>
      <dc:creator>hemwant</dc:creator>
      <dc:date>2021-11-01T07:05:26Z</dc:date>
    </item>
    <item>
      <title>Re: P1022: Console hangs after PCIE error dump</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1364934#M3942</link>
      <description>&lt;P&gt;PEXx_PEX_ERR_DR[PCT] is set&lt;/P&gt;
&lt;P&gt;PCI Express completion time-out. A completion time-out condition was detected for a non-posted,outbound PCI Express transaction. An error response is sent back to the requestor. Note that a completion timeout counter only starts when the non-posted request was able to send to the link partner.&lt;BR /&gt;1 A completion time-out on the PCI Express link was detected. Note that a completion timeout error is a fatal error. If a completion timeout error is detected, the system has become unstable. Hot reset is recommended to restore stability of the system.&lt;/P&gt;
&lt;P&gt;In general, &lt;STRONG&gt;completion&lt;/STRONG&gt; &lt;STRONG&gt;timeout&lt;/STRONG&gt; is caused by downstream EP device fails to send back the expected data for an outbound MRd. This normally happens when it's totally dead, since if it's just the case of an outbound MRd hitting an non-configured memory region of an EP, the EP should respond back with UR instead of silent&lt;/P&gt;</description>
      <pubDate>Tue, 02 Nov 2021 08:04:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1364934#M3942</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2021-11-02T08:04:08Z</dc:date>
    </item>
    <item>
      <title>Re: P1022: Console hangs after PCIE error dump</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1438684#M4121</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411"&gt;@yipingwang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can we avoid the CPU to go into inconsistent state in case of PCI Express completion time-out.&lt;/P&gt;&lt;P&gt;As per our understanding The CPU has to report the PCIe error and continue its process.&lt;/P&gt;&lt;P&gt;We need the Host CPU in running state to further debug and find out the root cause of the problem at framer device.&lt;/P&gt;</description>
      <pubDate>Tue, 05 Apr 2022 06:30:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1438684#M4121</guid>
      <dc:creator>hemwant</dc:creator>
      <dc:date>2022-04-05T06:30:59Z</dc:date>
    </item>
    <item>
      <title>Re: P1022: Console hangs after PCIE error dump</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1449593#M4137</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411"&gt;@yipingwang&lt;/a&gt;please respond to the queries raised in previous thread.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can we avoid the CPU to go into inconsistent state in case of PCI Express completion time-out.&lt;/P&gt;&lt;P&gt;As per our understanding The CPU has to report the PCIe error and continue its process.&lt;/P&gt;&lt;P&gt;We need the Host CPU in running state to further debug and find out the root cause of the problem at framer device.&lt;/P&gt;</description>
      <pubDate>Wed, 27 Apr 2022 05:00:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/P1022-Console-hangs-after-PCIE-error-dump/m-p/1449593#M4137</guid>
      <dc:creator>hemwant</dc:creator>
      <dc:date>2022-04-27T05:00:02Z</dc:date>
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