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    <title>PowerQUICC Processors中的主题 Re: PCIe enumeration issue in P1022</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1403034#M4062</link>
    <description>&lt;P&gt;We have checked the serdes lanes going to the link partner and its OK. Even the link partner is out of reset. There is no mistake in the serdes lane mapping as the issue is observed in 1 of the 11 prototype cards. Please let us know what we can look into further.&lt;/P&gt;</description>
    <pubDate>Fri, 21 Jan 2022 03:50:03 GMT</pubDate>
    <dc:creator>sarkarsouvik</dc:creator>
    <dc:date>2022-01-21T03:50:03Z</dc:date>
    <item>
      <title>PCIe enumeration issue in P1022</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1343894#M3877</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;We have a test card which successfully enumerates a PCIe endpoint device during startup. Now when a processor reboot is done without putting the endpoint-device in reset, the PCIe enumeration is lost.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now reading the&amp;nbsp; &lt;SPAN class="fontstyle0"&gt;LTSSM State Status Register on P1022, we found out that on the prototype cards where the enumeration is working, the value is read as 0x16. But in this card where the enumeration is lost on processor reboot, the value comes as 0x08 (Polling compliance as per page 1179 in P1022RM).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="fontstyle0"&gt;Please let me what is the issue. Your help in this regard is greatly appreciated.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Thanks and Regards,&lt;/P&gt;&lt;P&gt;Souvik&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2021 09:41:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1343894#M3877</guid>
      <dc:creator>sarkarsouvik</dc:creator>
      <dc:date>2021-09-22T09:41:08Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe enumeration issue in P1022</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1344004#M3878</link>
      <description>&lt;P&gt;If LTSSM is stuck at 0x08 (Polling.Compliance) -&amp;gt; possible "mistaken routing on SerDes lanes", or a dead transmitter from our remote link partner&lt;BR /&gt;- At least ONE lane previously detected a receiver never comes out of Electrical Idle&lt;BR /&gt;- Check remote link partner's transmitter and link routing. See if any extra "unexpected" lanes are wired to link partner. Terminate unused lane's receiver.&lt;/P&gt;</description>
      <pubDate>Wed, 22 Sep 2021 12:18:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1344004#M3878</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-09-22T12:18:25Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe enumeration issue in P1022</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1380972#M4006</link>
      <description>&lt;P&gt;We have checked the serdes lanes going to the link partner and its OK. Even the link partner is out of reset. There is no mistake in the serdes lane mapping as the issue is observed in 1 of the 11 prototype cards. Please let us know what we can look into further.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;</description>
      <pubDate>Fri, 03 Dec 2021 04:59:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1380972#M4006</guid>
      <dc:creator>sarkarsouvik</dc:creator>
      <dc:date>2021-12-03T04:59:05Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe enumeration issue in P1022</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1403034#M4062</link>
      <description>&lt;P&gt;We have checked the serdes lanes going to the link partner and its OK. Even the link partner is out of reset. There is no mistake in the serdes lane mapping as the issue is observed in 1 of the 11 prototype cards. Please let us know what we can look into further.&lt;/P&gt;</description>
      <pubDate>Fri, 21 Jan 2022 03:50:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/PCIe-enumeration-issue-in-P1022/m-p/1403034#M4062</guid>
      <dc:creator>sarkarsouvik</dc:creator>
      <dc:date>2022-01-21T03:50:03Z</dc:date>
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