https://community.nxp.com/t5/PowerQUICC-Processors/DDR4-LS1046A/m-p/1397875#M4059 <P>Hello NXP,</P><P>Can I configure DDR controller in LS1046A to 2T and 3T. If configured, what are precautions shall I consider.</P><P>Also what is the minimum master clock speed configuration&nbsp; allowed for DDR controller in LS1046A in DDR4 mode.</P> Wed, 12 Jan 2022 06:51:15 GMT Nareshvarikuntla 2022-01-12T06:51:15Z https://community.nxp.com/t5/PowerQUICC-Processors/DDR4-LS1046A/m-p/1397875#M4059 <P>Hello NXP,</P><P>Can I configure DDR controller in LS1046A to 2T and 3T. If configured, what are precautions shall I consider.</P><P>Also what is the minimum master clock speed configuration&nbsp; allowed for DDR controller in LS1046A in DDR4 mode.</P> Wed, 12 Jan 2022 06:51:15 GMT https://community.nxp.com/t5/PowerQUICC-Processors/DDR4-LS1046A/m-p/1397875#M4059 Nareshvarikuntla 2022-01-12T06:51:15Z https://community.nxp.com/t5/PowerQUICC-Processors/DDR4-LS1046A/m-p/1397899#M4060 <P>2T or 3T can be configured - refer to the LS1046A Reference Manual, 15.4.8 DDR SDRAM control configuration (DDR_SDRAM_CFG).</P> <P>&nbsp;</P> <P>2T (T2_EN) should not be set if DDR_SDRAM_CFG[T3_EN] is set.</P> <P>Note that RD_EN and T2_EN must not both be set at the same time.</P> <P>&nbsp;</P> <P>3T (T3_EN) cannot be set if DDR_SDRAM_CFG[T2_EN] is also set.</P> <P>3T timing may not be used with 4-beat bursts, unless DDR_SDRAM_CFG_2[OBC_CFG] is set.</P> <P>&nbsp;</P> <P>Lowest supported Memory Bus Clock Frequency (DDR4) is 650 MHz - refer to the QorIQ LS1046A, LS1026A Data Sheet, Table 140. Processor, platform, and memory clocking specifications.</P> Wed, 12 Jan 2022 07:23:49 GMT https://community.nxp.com/t5/PowerQUICC-Processors/DDR4-LS1046A/m-p/1397899#M4060 ufedor 2022-01-12T07:23:49Z