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    <title>topic LS1046A DDR4 interface in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/LS1046A-DDR4-interface/m-p/1393299#M4048</link>
    <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;Can I interface just 32 bit DDR4 with ECC memory to LS1046A. Could please provide references in this regard.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Naresh V.&lt;/P&gt;</description>
    <pubDate>Thu, 30 Dec 2021 08:46:42 GMT</pubDate>
    <dc:creator>Nareshvarikuntla</dc:creator>
    <dc:date>2021-12-30T08:46:42Z</dc:date>
    <item>
      <title>LS1046A DDR4 interface</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/LS1046A-DDR4-interface/m-p/1393299#M4048</link>
      <description>&lt;P&gt;Dear NXP,&lt;/P&gt;&lt;P&gt;Can I interface just 32 bit DDR4 with ECC memory to LS1046A. Could please provide references in this regard.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Naresh V.&lt;/P&gt;</description>
      <pubDate>Thu, 30 Dec 2021 08:46:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/LS1046A-DDR4-interface/m-p/1393299#M4048</guid>
      <dc:creator>Nareshvarikuntla</dc:creator>
      <dc:date>2021-12-30T08:46:42Z</dc:date>
    </item>
    <item>
      <title>Re: LS1046A DDR4 interface</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/LS1046A-DDR4-interface/m-p/1393448#M4049</link>
      <description>&lt;P&gt;&amp;gt; Can I interface just 32 bit DDR4 with ECC memory to LS1046A.&lt;/P&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;P&gt;&amp;gt; Could please provide references in this regard.&lt;/P&gt;&lt;P&gt;Please refer to the FRWY-LS1046A schematics available at:&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A?fpsp=1#Design-Resources" target="_blank"&gt;https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A?fpsp=1#Design-Resources&lt;/A&gt;&lt;/P&gt;&lt;P&gt;For 32-bit case do not implement U17 and U18.&lt;/P&gt;&lt;P&gt;Assuming that Accumulated ECC will be enabled, D1_MECC[4-7] have to be left unconnected.&lt;/P&gt;</description>
      <pubDate>Fri, 31 Dec 2021 03:35:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/LS1046A-DDR4-interface/m-p/1393448#M4049</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-12-31T03:35:33Z</dc:date>
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